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| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2014-06-27 14:39:31 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-07-22 16:25:55 -0700 |
| commit | e55782ecccadc196a4f9d8e5e8b456e200ea9727 (patch) | |
| tree | 3d4dcbee135b3765763fb876e02a6e34299502e9 /board/freescale | |
| parent | 3d75ec95f57224995210db5c5dea8d458cf862fb (diff) | |
| download | u-boot-imx-e55782ecccadc196a4f9d8e5e8b456e200ea9727.zip u-boot-imx-e55782ecccadc196a4f9d8e5e8b456e200ea9727.tar.gz u-boot-imx-e55782ecccadc196a4f9d8e5e8b456e200ea9727.tar.bz2 | |
powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs.
We use PLL1CR0 to check the serdes reference clock.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/t4qds/t4240qds.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index c5161c8..6205fea 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -644,9 +644,10 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; u32 actual[MAX_SERDES]; + u32 pllcr0, expected; unsigned int i; sw = QIXIS_READ(brdcfg[2]); @@ -669,8 +670,9 @@ int misc_init_r(void) } for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), |