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authorChunhe Lan <Chunhe.Lan@freescale.com>2014-05-20 13:34:28 +0800
committerYork Sun <yorksun@freescale.com>2014-06-05 12:56:13 -0700
commite6c334a7a4d90b399d2280105146378194b5f5f1 (patch)
treea6d1fcda5c7d7c13b3c866498970e995bb2545d0 /board/freescale
parent40483e1e1d8f87527a1cba37e4641877b890b700 (diff)
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powerpc/t4rdb: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. The protocols only using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. Alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/t4rdb/eth.c2
-rw-r--r--board/freescale/t4rdb/t4_rcw.cfg4
2 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475..142c6a8 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index 13408bd..fdbbe5e 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 28_56_2_10
+#serdes protocol 27_56_1_9
16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028