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authorTom Rini <trini@ti.com>2014-02-25 12:44:13 -0500
committerTom Rini <trini@ti.com>2014-02-25 13:55:49 -0500
commita7e8c15f71456d55ccb27f843862af03a00e0957 (patch)
tree67028131161fdded15fd8625aabf3de03cc98b00 /board/freescale
parent4c48cfb58b66924c52cd5c5d960e04cf6d7064ca (diff)
parent91d7746df89f858548fe535137b4b185a6a76d59 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/p1010rdb/Makefile4
-rw-r--r--board/freescale/p1010rdb/spl.c108
-rw-r--r--board/freescale/p1010rdb/spl_minimal.c76
-rw-r--r--board/freescale/p1010rdb/tlb.c12
-rw-r--r--board/freescale/t208xqds/Makefile (renamed from board/freescale/t2080qds/Makefile)6
-rw-r--r--board/freescale/t208xqds/ddr.c (renamed from board/freescale/t2080qds/ddr.c)0
-rw-r--r--board/freescale/t208xqds/ddr.h (renamed from board/freescale/t2080qds/ddr.h)0
-rw-r--r--board/freescale/t208xqds/eth_t208xqds.c (renamed from board/freescale/t2080qds/eth_t2080qds.c)219
-rw-r--r--board/freescale/t208xqds/law.c (renamed from board/freescale/t2080qds/law.c)0
-rw-r--r--board/freescale/t208xqds/pci.c (renamed from board/freescale/t2080qds/pci.c)0
-rw-r--r--board/freescale/t208xqds/t2080_rcw.cfg (renamed from board/freescale/t2080qds/t2080_rcw.cfg)0
-rw-r--r--board/freescale/t208xqds/t2081_rcw.cfg8
-rw-r--r--board/freescale/t208xqds/t208x_pbi.cfg (renamed from board/freescale/t2080qds/t2080_pbi.cfg)0
-rw-r--r--board/freescale/t208xqds/t208xqds.c (renamed from board/freescale/t2080qds/t2080qds.c)89
-rw-r--r--board/freescale/t208xqds/t208xqds.h (renamed from board/freescale/t2080qds/t2080qds.h)0
-rw-r--r--board/freescale/t208xqds/t208xqds_qixis.h (renamed from board/freescale/t2080qds/t2080qds_qixis.h)8
-rw-r--r--board/freescale/t208xqds/tlb.c (renamed from board/freescale/t2080qds/tlb.c)0
17 files changed, 405 insertions, 125 deletions
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index d6f05f3..660d1bb 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -18,6 +18,10 @@ obj-y += spl_minimal.o tlb.o law.o
else
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
+
obj-y += p1010rdb.o
obj-y += ddr.o
obj-y += law.o
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
new file mode 100644
index 0000000..11bd9cf
--- /dev/null
+++ b/board/freescale/p1010rdb/spl.c
@@ -0,0 +1,108 @@
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ console_init_f();
+
+ /* Clock configuration to access CPLD using IFC(GPCM) */
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+#ifdef CONFIG_P1010RDB_PB
+ setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ puts("\nSPI Flash boot...\n");
+#endif
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+ bd_t *bd;
+
+ memset(gd, 0, sizeof(gd_t));
+ bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+ probecpu();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+ env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_initialize(bd);
+#endif
+
+ /* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+#else
+ env_relocate();
+#endif
+
+ i2c_init_all();
+
+ gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts("\nTertiary program loader running in sram...");
+#else
+ puts("\nSecond program loader running in sram...");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+ mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+ spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
+#endif
+}
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index 39a5a0f..6079570 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -16,78 +16,16 @@
DECLARE_GLOBAL_DATA_PTR;
-
-void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 ddr_ratio;
- unsigned long ddr_freq_mhz;
-
- ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
- ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
-
- /* mask off E bit */
- u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-
- if (ddr_freq_mhz < 700) {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl);
- } else {
- __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
- }
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
- /* P1014 and it's derivatives support max 16bit DDR width */
- if (svr == SVR_P1014) {
- __raw_writel(ddr->sdram_cfg & ~SDRAM_CFG_DBW_MASK, &ddr->sdram_cfg);
- __raw_writel(ddr->sdram_cfg | SDRAM_CFG_16_BE, &ddr->sdram_cfg);
- /* For CS0_BNDS we divide the start and end address by 2, so we can just
- * shift the entire register to achieve the desired result and the mask
- * the value so we don't write reserved fields */
- __raw_writel((CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff, &ddr->cs0_bnds);
- }
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
+
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
@@ -98,9 +36,6 @@ void board_init_f(ulong bootflag)
puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
-
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
@@ -111,6 +46,7 @@ void board_init_f(ulong bootflag)
void board_init_r(gd_t *gd, ulong dest_addr)
{
+ puts("\nSecond program loader running in sram...");
nand_boot();
}
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index a3d36b3..af40f97 100644
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -73,10 +73,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 8, BOOKE_PAGESZ_1G, 1)
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};
diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t208xqds/Makefile
index 0b8747b..947b7f7 100644
--- a/board/freescale/t2080qds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -4,8 +4,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_T2080QDS) += t2080qds.o
-obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o
+obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o
+obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
obj-$(CONFIG_PCI) += pci.o
obj-y += ddr.o
obj-y += law.o
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t208xqds/ddr.c
index ed1334d..ed1334d 100644
--- a/board/freescale/t2080qds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9fc879a..9fc879a 100644
--- a/board/freescale/t2080qds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t208xqds/eth_t208xqds.c
index 3e4ab8f..7d8411b 100644
--- a/board/freescale/t2080qds/eth_t2080qds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -25,21 +25,30 @@
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
+#if defined(CONFIG_T2080QDS)
#define EMI1_SLOT2 6
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
-#define EMI2 7
+#elif defined(CONFIG_T2081QDS)
+#define EMI1_SLOT2 3
+#define EMI1_SLOT3 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT6 6
+#define EMI1_SLOT7 7
+#endif
+#define EMI2 8
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
+#if defined(CONFIG_T2080QDS)
"T2080QDS_MDIO_RGMII1",
"T2080QDS_MDIO_RGMII2",
"T2080QDS_MDIO_SLOT1",
@@ -48,12 +57,27 @@ static const char * const mdio_names[] = {
"T2080QDS_MDIO_SLOT5",
"T2080QDS_MDIO_SLOT2",
"T2080QDS_MDIO_10GC",
+#elif defined(CONFIG_T2081QDS)
+ "T2081QDS_MDIO_RGMII1",
+ "T2081QDS_MDIO_RGMII2",
+ "T2081QDS_MDIO_SLOT1",
+ "T2081QDS_MDIO_SLOT2",
+ "T2081QDS_MDIO_SLOT3",
+ "T2081QDS_MDIO_SLOT5",
+ "T2081QDS_MDIO_SLOT6",
+ "T2081QDS_MDIO_SLOT7",
+ "T2081QDS_MDIO_10GC",
+#endif
};
/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+#if defined(CONFIG_T2080QDS)
static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+#elif defined(CONFIG_T2081QDS)
+static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
+#endif
-static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
@@ -61,7 +85,7 @@ static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
- const char *name = T2080qds_mdio_name_for_muxval(muxval);
+ const char *name = t208xqds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
@@ -78,15 +102,15 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval)
return bus;
}
-struct T2080qds_mdio {
+struct t208xqds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
-static void T2080qds_mux_mdio(u8 muxval)
+static void t208xqds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
- if (muxval < 7) {
+ if (muxval < 8) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
@@ -94,54 +118,54 @@ static void T2080qds_mux_mdio(u8 muxval)
}
}
-static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
-static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
- T2080qds_mux_mdio(priv->muxval);
+ t208xqds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
-static int T2080qds_mdio_reset(struct mii_dev *bus)
+static int t208xqds_mdio_reset(struct mii_dev *bus)
{
- struct T2080qds_mdio *priv = bus->priv;
+ struct t208xqds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
-static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+static int t208xqds_mdio_init(char *realbusname, u8 muxval)
{
- struct T2080qds_mdio *pmdio;
+ struct t208xqds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
- printf("Failed to allocate T2080QDS MDIO bus\n");
+ printf("Failed to allocate t208xqds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
- printf("Failed to allocate T2080QDS private data\n");
+ printf("Failed to allocate t208xqds private data\n");
free(bus);
return -1;
}
- bus->read = T2080qds_mdio_read;
- bus->write = T2080qds_mdio_write;
- bus->reset = T2080qds_mdio_reset;
- sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+ bus->read = t208xqds_mdio_read;
+ bus->write = t208xqds_mdio_write;
+ bus->reset = t208xqds_mdio_reset;
+ sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
@@ -154,7 +178,6 @@ static int T2080qds_mdio_init(char *realbusname, u8 muxval)
pmdio->muxval = muxval;
bus->priv = pmdio;
-
return mdio_register(bus);
}
@@ -173,13 +196,20 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
switch (port) {
+#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC9:
case FM1_DTSEC10:
- sprintf(alias, "phy_sgmii_s3_%x", phy);
- fdt_set_phy_handle(fdt, compat, addr, alias);
- fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ }
break;
case FM1_DTSEC5:
case FM1_DTSEC6:
@@ -193,6 +223,36 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
fdt_status_okay_by_alias(fdt, "emi1_slot2");
}
break;
+#elif defined(CONFIG_T2081QDS)
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ } else if (mdio_mux[port] == EMI1_SLOT3) {
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ } else if (mdio_mux[port] == EMI1_SLOT5) {
+ sprintf(alias, "phy_sgmii_s5_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot5");
+ } else if (mdio_mux[port] == EMI1_SLOT6) {
+ sprintf(alias, "phy_sgmii_s6_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot6");
+ } else if (mdio_mux[port] == EMI1_SLOT7) {
+ sprintf(alias, "phy_sgmii_s7_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot7");
+ }
+ break;
+#endif
default:
break;
}
@@ -226,8 +286,8 @@ void fdt_fixup_board_enet(void *fdt)
}
/*
- * This function reads RCW to check if Serdes1{E,F,G,H} is configured
- * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ * This function reads RCW to check if Serdes1{A:H} is configured
+ * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
*/
static void initialize_lane_to_slot(void)
{
@@ -238,6 +298,7 @@ static void initialize_lane_to_slot(void)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
+#if defined(CONFIG_T2080QDS)
case 0x51:
case 0x5f:
case 0x65:
@@ -264,6 +325,31 @@ static void initialize_lane_to_slot(void)
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x6b:
+ lane_to_slot[4] = 1;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xca:
+ case 0xcb:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 6;
+ lane_to_slot[3] = 5;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ case 0xf2:
+ lane_to_slot[1] = 7;
+ lane_to_slot[2] = 7;
+ lane_to_slot[3] = 7;
+ lane_to_slot[5] = 4;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 7;
+ break;
+#endif
default:
break;
}
@@ -305,14 +391,20 @@ int board_eth_init(bd_t *bis)
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
- T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
- T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+#if defined(CONFIG_T2080QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+#if defined(CONFIG_T2081QDS)
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
+ t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+#endif
+ t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
@@ -327,21 +419,21 @@ int board_eth_init(bd_t *bis)
case 0x95:
case 0xa2:
case 0x94:
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x51:
case 0x5f:
case 0x65:
- /* XAUI/HiGig in Slot3 */
+ /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
@@ -365,7 +457,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
- /* SGMII in Slot2 */
+ /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
@@ -373,7 +465,7 @@ int board_eth_init(bd_t *bis)
case 0x6d:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
- /* SGMII in Slot3 */
+ /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
@@ -408,6 +500,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
+#if defined(CONFIG_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
@@ -419,6 +512,27 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0xca:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ /* SGMII in Slot5 */
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot6 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ /* SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ break;
+#endif
+ case 0xf2:
+ /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
default:
break;
}
@@ -452,8 +566,25 @@ int board_eth_init(bd_t *bis)
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
- mdio_mux[i]));
+ mdio_mux[i]));
+ break;
+#if defined(CONFIG_T2081QDS)
+ case 5:
+ mdio_mux[i] = EMI1_SLOT5;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 6:
+ mdio_mux[i] = EMI1_SLOT6;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 7:
+ mdio_mux[i] = EMI1_SLOT7;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
break;
+#endif
}
break;
case PHY_INTERFACE_MODE_RGMII:
diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t208xqds/law.c
index 74e2a53..74e2a53 100644
--- a/board/freescale/t2080qds/law.c
+++ b/board/freescale/t208xqds/law.c
diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t208xqds/pci.c
index 84a89da..84a89da 100644
--- a/board/freescale/t2080qds/pci.c
+++ b/board/freescale/t208xqds/pci.c
diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index c2ad0fd..c2ad0fd 100644
--- a/board/freescale/t2080qds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_rcw.cfg
new file mode 100644
index 0000000..a2d5ecf
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
index e200d92..e200d92 100644
--- a/board/freescale/t2080qds/t2080_pbi.cfg
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t208xqds/t208xqds.c
index 4fe8ccb..9cfc0bd 100644
--- a/board/freescale/t2080qds/t2080qds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -20,8 +20,8 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
-#include "t2080qds.h"
-#include "t2080qds_qixis.h"
+#include "t208xqds.h"
+#include "t208xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -89,19 +89,22 @@ int select_i2c_ch_pca9547(u8 ch)
int brd_mux_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 srds_prtcl_s1, srds_prtcl_s2;
+ u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
- srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+#if defined(CONFIG_T2080QDS)
+ u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+#endif
switch (srds_prtcl_s1) {
case 0:
/* SerDes1 is not enabled */
break;
+#if defined(CONFIG_T2080QDS)
case 0x1c:
case 0xa2:
/* SD1(A:D) => SLOT3 SGMII
@@ -180,12 +183,89 @@ int brd_mux_lane_to_slot(void)
*/
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
+#elif defined(CONFIG_T2081QDS)
+ case 0x51:
+ /* SD1(A:D) => SLOT2 XAUI
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6b:
+ /* SD1(A:D) => XFI SFP Module
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x6c:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0x6d:
+ /* SD1(A:B) => XFI SFP Module
+ * SD1(C:D) => SLOT2 SGMII
+ * SD1(E:H) => SLOT1 PCIe4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xe8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xaa:
+ case 0xab:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(F:H) => SLOT1 SGMI4 x4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf8);
+ QIXIS_WRITE(brdcfg[13], 0x0);
+ break;
+ case 0xca:
+ case 0xcb:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B) => SLOT7 SGMII
+ * SD1(C) => SLOT6 SGMII
+ * SD1(D) => SLOT5 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F:H) => SLOT3 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x80);
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0xde:
+ case 0xdf:
+ /* SD1(A:D) => SLOT2 PCIe3 x4
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x98);
+ QIXIS_WRITE(brdcfg[13], 0x25);
+ break;
+ case 0xf2:
+ /* SD1(A) => SLOT2 PCIe3 x1
+ * SD1(B:D) => SLOT7 SGMII
+ * SD1(E) => SLOT1 PCIe4 x1
+ * SD1(F) => SLOT4 PCIe1 x1
+ * SD1(G) => SLOT3 PCIe2 x1
+ * SD1(H) => SLOT7 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x81);
+ QIXIS_WRITE(brdcfg[13], 0xa5);
+ break;
+#endif
default:
printf("WARNING: unsupported for SerDes1 Protocol %d\n",
srds_prtcl_s1);
return -1;
}
+#ifdef CONFIG_T2080QDS
switch (srds_prtcl_s2) {
case 0:
/* SerDes2 is not enabled */
@@ -241,6 +321,7 @@ int brd_mux_lane_to_slot(void)
srds_prtcl_s2);
return -1;
}
+#endif
return 0;
}
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t208xqds/t208xqds.h
index 39fcef2..39fcef2 100644
--- a/board/freescale/t2080qds/t2080qds.h
+++ b/board/freescale/t208xqds/t208xqds.h
diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
index fc83da7..bdcdc12 100644
--- a/board/freescale/t2080qds/t2080qds_qixis.h
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __T2080QDS_QIXIS_H__
-#define __T2080QDS_QIXIS_H__
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
-/* Definitions of QIXIS Registers for T2080QDS */
+/* Definitions of QIXIS Registers for T208xQDS */
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
@@ -35,6 +35,8 @@
#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+#define BRDCFG9_SFP_TX_EN 0x10
+
#define BRDCFG12_SD3EN_MASK 0x20
#define BRDCFG12_SD3MX_MASK 0x08
#define BRDCFG12_SD3MX_SLOT5 0x08
diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t208xqds/tlb.c
index 62cd110..62cd110 100644
--- a/board/freescale/t2080qds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c