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authorDave Liu <daveliu@freescale.com>2009-12-16 10:24:39 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-05 13:50:07 -0600
commit3e731aaba30c7011edf6391072eee845ed1b816f (patch)
treeff32b3e1f2bbec7abfcd740f4dda254bd92cf0ab /board/freescale
parent1aa3d08a0244506b94031522e54fe06ee7a5ae0e (diff)
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fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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