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| author | Adrian Alonso <adrian.alonso@nxp.com> | 2016-02-09 10:25:58 -0600 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2016-05-23 15:43:32 -0500 |
| commit | 148ec2bf7053e093fda5598077acd41323721ee9 (patch) | |
| tree | a10fece30f1ba6ef5b360428dc4f7b53962189ec /board/freescale | |
| parent | 4797d83b0b259101cc417e6d302c8717201a4d2c (diff) | |
| download | u-boot-imx-148ec2bf7053e093fda5598077acd41323721ee9.zip u-boot-imx-148ec2bf7053e093fda5598077acd41323721ee9.tar.gz u-boot-imx-148ec2bf7053e093fda5598077acd41323721ee9.tar.bz2 | |
MLK-12393: imx: mx6qamr2: update lpddr2 dcd programming aid settings
Adjust optimal valid clock cycles for 400Mhz operation
Adjust valid clock cycles before self-refresh exit tCKSRX
Adjust valid clock cycles after self-refresh entry tCKSRE
Set MMDC1_MPZQHWCCTRL upper 16 bits to default reset value
DDR calibration script
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69
Test result: Stress test passed.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx6qarm2/mt128x64mx32.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg index 3c49b48..adc8c4b 100644 --- a/board/freescale/mx6qarm2/mt128x64mx32.cfg +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -143,7 +143,7 @@ DATA 4 0x021b485c 0x1b5f0109 //LPDDR2 ZQ params // //============================================================================= DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration -DATA 4 0x021b4800 0xa1310003 // DDR_PHY_P1_MPZQHWCTRL +DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL DATA 4 0x021b0890 0x00400000 //ca bus abs delay DATA 4 0x021b4890 0x00400000 //ca bus abs delay @@ -196,7 +196,7 @@ DATA 4 0x021b48b8 0x00000800 //frc_msr. // Channel0 - starting address 0x80000000 DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 -DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC +DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 @@ -216,7 +216,7 @@ DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL // Channel1 - starting address 0x10000000 // Note: the values for Chan1 should match those of Chan0 DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0 -DATA 4 0x021b4004 0x00020036 // MMDC1_MDPDC +DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1 DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2 DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC @@ -276,8 +276,8 @@ DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr -DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC now SDCTL power down enabled -DATA 4 0x021b4004 0x00025576 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting +DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled +DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting |