Merge remote-tracking branch 'u-boot/master'

41 files changed, 503 insertions, 1876 deletions

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 0b40dc7..54cb098 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -51,14 +51,12 @@ COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
 COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
-COBJS-$(CONFIG_P3060QDS)       	+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
 
 # deal with common files for P-series corenet based devices
 SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
-SUBLIB-$(CONFIG_P3060QDS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
 
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 6ddf816..3ef4936 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -25,6 +25,9 @@
 #include <libfdt_env.h>
 #include <fdt_support.h>
 
+#include <fm_eth.h>
+#include <asm/fsl_serdes.h>
+
 /*
  * Given the following ...
  *
@@ -67,3 +70,31 @@ int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
 
 	return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
 }
+
+/*
+ * Return the SerDes device enum for a given Fman port
+ *
+ * This function just maps the fm_port namespace to the srds_prtcl namespace.
+ */
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port)
+{
+	static const enum srds_prtcl srds_table[] = {
+		[FM1_DTSEC1] = SGMII_FM1_DTSEC1,
+		[FM1_DTSEC2] = SGMII_FM1_DTSEC2,
+		[FM1_DTSEC3] = SGMII_FM1_DTSEC3,
+		[FM1_DTSEC4] = SGMII_FM1_DTSEC4,
+		[FM1_DTSEC5] = SGMII_FM1_DTSEC5,
+		[FM1_10GEC1] = XAUI_FM1,
+		[FM2_DTSEC1] = SGMII_FM2_DTSEC1,
+		[FM2_DTSEC2] = SGMII_FM2_DTSEC2,
+		[FM2_DTSEC3] = SGMII_FM2_DTSEC3,
+		[FM2_DTSEC4] = SGMII_FM2_DTSEC4,
+		[FM2_DTSEC5] = SGMII_FM2_DTSEC5,
+		[FM2_10GEC1] = XAUI_FM2,
+	};
+
+	if ((port < FM1_DTSEC1) || (port > FM2_10GEC1))
+		return NONE;
+	else
+		return srds_table[port];
+}
diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h
index d39ef08..734b1da 100644
--- a/board/freescale/common/fman.h
+++ b/board/freescale/common/fman.h
@@ -23,4 +23,6 @@
 int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr,
 			const char *alias);
 
+enum srds_prtcl serdes_device_from_fm_port(enum fm_port port);
+
 #endif
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index c4566dd..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,19 +48,6 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
-#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
-	SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
-				LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-	SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
-				LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
-	SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
-				LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-	SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
-				LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
-#endif
-#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index da21627..e5cf208 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,13 +66,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
-#elif defined(CONFIG_SRIOBOOT_SLAVE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 	/*
-	 * SRIOBOOT-SLAVE. When slave boot, the address of the
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
 	 * space is at 0xfff00000, it covered the 0xfffff000.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
-			CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+			CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
@@ -147,13 +147,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 16, BOOKE_PAGESZ_1M, 1),
 #endif
-#ifdef CONFIG_SRIOBOOT_SLAVE
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 	/*
-	 * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
-	 * and ENV from master
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
-		CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		0, 17, BOOKE_PAGESZ_1M, 1),
 #endif
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index b87b092..2c69c51 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -68,6 +68,15 @@ static char *mdio_names[16] = {
 	NULL, NULL, NULL,
 };
 
+/*
+ * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot.
+ */
+static u8 lane_to_slot[] = {
+	1, 1, 2, 2, 3, 3, 3, 3, 6, 6, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
 static char *p4080ds_mdio_name_for_muxval(u32 muxval)
 {
 	return mdio_names[(muxval & EMI_MASK) >> 28];
@@ -290,15 +299,6 @@ void fdt_fixup_board_enet(void *fdt)
 	}
 }
 
-enum board_slots {
-	SLOT1 = 1,
-	SLOT2,
-	SLOT3,
-	SLOT4,
-	SLOT5,
-	SLOT6,
-};
-
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
@@ -307,27 +307,6 @@ int board_eth_init(bd_t *bis)
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
 
-	u8 lane_to_slot[] = {
-		SLOT1, /* 0 - Bank 1:A */
-		SLOT1, /* 1 - Bank 1:B */
-		SLOT2, /* 2 - Bank 1:C */
-		SLOT2, /* 3 - Bank 1:D */
-		SLOT3, /* 4 - Bank 1:E */
-		SLOT3, /* 5 - Bank 1:F */
-		SLOT3, /* 6 - Bank 1:G */
-		SLOT3, /* 7 - Bank 1:H */
-		SLOT6, /* 8 - Bank 1:I */
-		SLOT6, /* 9 - Bank 1:J */
-		SLOT4, /* 10 - Bank 2:A */
-		SLOT4, /* 11 - Bank 2:B */
-		SLOT4, /* 12 - Bank 2:C */
-		SLOT4, /* 13 - Bank 2:D */
-		SLOT5, /* 14 - Bank 3:A */
-		SLOT5, /* 15 - Bank 3:B */
-		SLOT5, /* 16 - Bank 3:C */
-		SLOT5, /* 17 - Bank 3:D */
-	};
-
 	/* Initialize the mdio_mux array so we can recognize empty elements */
 	for (i = 0; i < NUM_FM_PORTS; i++)
 		mdio_mux[i] = EMI_NONE;
@@ -380,17 +359,17 @@ int board_eth_init(bd_t *bis)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
-			case SLOT3:
+			case 3:
 				mdio_mux[i] = EMI1_SLOT3;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT4:
+			case 4:
 				mdio_mux[i] = EMI1_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT5:
+			case 5:
 				mdio_mux[i] = EMI1_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
@@ -417,12 +396,12 @@ int board_eth_init(bd_t *bis)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
-			case SLOT4:
+			case 4:
 				mdio_mux[i] = EMI2_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT5:
+			case 5:
 				mdio_mux[i] = EMI2_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
@@ -444,17 +423,17 @@ int board_eth_init(bd_t *bis)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
-			case SLOT3:
+			case 3:
 				mdio_mux[i] = EMI1_SLOT3;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT4:
+			case 4:
 				mdio_mux[i] = EMI1_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT5:
+			case 5:
 				mdio_mux[i] = EMI1_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
@@ -481,12 +460,12 @@ int board_eth_init(bd_t *bis)
 				break;
 			slot = lane_to_slot[lane];
 			switch (slot) {
-			case SLOT4:
+			case 4:
 				mdio_mux[i] = EMI2_SLOT4;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
 				break;
-			case SLOT5:
+			case 5:
 				mdio_mux[i] = EMI2_SLOT5;
 				fm_info_set_mdio(i,
 					mii_dev_for_muxval(mdio_mux[i]));
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
new file mode 100644
index 0000000..50806ca
--- /dev/null
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -0,0 +1,51 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1 as 1MB SRAM
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/corenet_ds/rcw_p3041ds.cfg b/board/freescale/corenet_ds/rcw_p3041ds.cfg
new file mode 100644
index 0000000..8813156
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p3041ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P3041DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p4080ds.cfg b/board/freescale/corenet_ds/rcw_p4080ds.cfg
new file mode 100644
index 0000000..6a26339
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p4080ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P4080DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+105a0000 00000000 1e1e181e 0000cccc
+58400000 3c3c2000 58000000 e1000000
+00000000 00000000 00000000 008b6000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg
new file mode 100644
index 0000000..b09e409
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5020ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5020DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0C540000 00000000 1E120000 00000000
+D8984A01 03002000 58000000 41000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 5f99e2f..355cfed 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,7 +40,7 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
 #ifdef CONFIG_SYS_SDRAM_BASE1
-	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
 #endif
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 	asm("nop");
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
 	asm("nop");
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 	asm("nop");
 
 	udelay(100);
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index 9109edb..a9bec58 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -59,36 +60,37 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
 	__asm__("nop");
 
 	udelay(1000);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 #endif
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index b9e6126..e9a568e 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,8 +40,8 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 dramsize, i, dramclk;
 
 	/*
@@ -48,14 +49,15 @@ phys_size_t initdram(int board_type)
 	 * the port-size of SDRAM.  In this case it is necessary to enable
 	 * Data[15:0] on Port Address/Data.
 	 */
-	gpio->par_ad =
-	    GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
-	    GPIO_PAR_AD_DATAL;
+	out_8(&gpio->par_ad,
+		GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+		GPIO_PAR_AD_DATAL);
 
 	/* Initialize PAR to enable SDRAM signals */
-	gpio->par_sdram =
-	    GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
-	    GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+	out_8(&gpio->par_sdram,
+		GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+		GPIO_PAR_SDRAM_SDCS(3));
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
@@ -64,25 +66,28 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+	if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
 		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
 
 		/* Initialize DRAM Control Register: DCR */
-		sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
-		    SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+		out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+			SDRAMC_DCR_RTIM_6CLKS |
+			SDRAMC_DCR_RC((15 * dramclk) >> 4));
 
 		/* Initialize DACR0 */
-		sdram->dacr0 =
-		    SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
-		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+		out_be32(&sdram->dacr0,
+			SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+			SDRAMC_DARCn_PS_32);
 		asm("nop");
 
 		/* Initialize DMR0 */
-		sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+		out_be32(&sdram->dmr0,
+			((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
 		asm("nop");
 
 		/* Set IP (bit 3) in DACR */
-		sdram->dacr0 |= SDRAMC_DARCn_IP;
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
 
 		/* Wait 30ns to allow banks to precharge */
 		for (i = 0; i < 5; i++) {
@@ -93,7 +98,7 @@ phys_size_t initdram(int board_type)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
 
 		/*  Set RE (bit 15) in DACR */
-		sdram->dacr0 |= SDRAMC_DARCn_RE;
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
 
 		/* Wait for at least 8 auto refresh cycles to occur */
 		for (i = 0; i < 0x2000; i++) {
@@ -101,7 +106,7 @@ phys_size_t initdram(int board_type)
 		}
 
 		/* Finish the configuration by issuing the MRS. */
-		sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
 		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 8ffb2cc..052993d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -109,7 +109,7 @@ int ide_preinit(void)
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -120,7 +120,8 @@ void ide_set_reset(int idereset)
 	};
 
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -129,17 +130,19 @@ void ide_set_reset(int idereset)
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
-
-		ata->cr = 0x40;	/* IORDY enable */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index ae69f67..658748b 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int checkboard(void)
 {
@@ -101,7 +102,7 @@ int ide_preinit(void)
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+	atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -112,7 +113,8 @@ void ide_set_reset(int idereset)
 	};
 
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(100);
 	} else {
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -121,17 +123,19 @@ void ide_set_reset(int idereset)
 		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
-
-		ata->cr = 0x40;	/* IORDY enable */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(2000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif				/* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 902ca3a..c3160ce 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -2,6 +2,8 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -23,6 +25,7 @@
 
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 
 int checkboard (void) {
@@ -32,10 +35,10 @@ int checkboard (void) {
 	};
 
 phys_size_t initdram (int board_type) {
-	volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
-	sdp->sdram_sdtr = 0xf539;
-	sdp->sdram_sdcr = 0x4211;
+	out_be16(&sdp->sdram_sdtr, 0xf539);
+	out_be16(&sdp->sdram_sdcr, 0x4211);
 
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 35c9b20..1bbe5a3 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -4,6 +4,8 @@
  *
  * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -25,6 +27,7 @@
 
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #define PERIOD		13	/* system bus period in ns */
 #define SDRAM_TREFI	7800	/* in ns */
@@ -38,67 +41,68 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
 
-	gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+	/* Enable SDRAM */
+	out_be16(&gpio_reg->par_sdram, 0x3FF);
 
 	/* Set up chip select */
-	sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
-	sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+	out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+	out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
 
 	/* Set up timing */
-	sdp->sdcfg1 = 0x83711630;
-	sdp->sdcfg2 = 0x46770000;
+	out_be32(&sdp->sdcfg1, 0x83711630);
+	out_be32(&sdp->sdcfg2, 0x46770000);
 
 	/* Enable clock */
-	sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+	out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
 
 	/* Set precharge */
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
 
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LEMR */
-	sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
-			| MCF_SDRAMC_SDMR_AD(0x0)
-			| MCF_SDRAMC_SDMR_CMD;
+	setbits_be32(&sdp->sdmr,
+		MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+		MCF_SDRAMC_SDMR_CMD);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LMR */
-	sdp->sdmr = 0x058d0000;
+	out_be32(&sdp->sdmr, 0x058d0000);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
-	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
 
 	/* Set precharge */
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop manual precharge, send 2 IREF */
-	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
-	sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+	setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
-	/* Write mode register, clear reset DLL */
-	sdp->sdmr = 0x018d0000;
+
+	out_be32(&sdp->sdmr, 0x018d0000);
 	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
-	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
-	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+	clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+	clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
 
 	/* Turn on auto refresh, lock SDMR */
-	sdp->sdcr =
+	out_be32(&sdp->sdcr,
 		MCF_SDRAMC_SDCR_CKE
 		| MCF_SDRAMC_SDCR_REF
 		| MCF_SDRAMC_SDCR_MUX(1)
 		/* 1 added to round up */
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
-		| MCF_SDRAMC_SDCR_DQS_OE(0x3);
+		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
 
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index f331786..142485f 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,7 +40,7 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
 #ifdef CONFIG_SYS_SDRAM_BASE1
-	sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
 #endif
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 	asm("nop");
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 	asm("nop");
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
 	asm("nop");
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 	asm("nop");
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 	asm("nop");
 
 	udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index b4df22f..1c14b83 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,7 +40,7 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
-	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 16025f9..c70c98c 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/*
 	 * set up pin configuration - enabled 2nd output buffer's signals
 	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
 	 * to use nCE signal
 	 */
-	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
-	gpio->pddr_timer |= 0x08;
-	gpio->ppd_timer |= 0x08;
-	gpio->pclrr_timer = 0;
-	gpio->podr_timer = 0;
+	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+	setbits_8(&gpio->pddr_timer, 0x08);
+	setbits_8(&gpio->ppd_timer, 0x08);
+	out_8(&gpio->pclrr_timer, 0);
+	out_8(&gpio->podr_timer, 0);
 
 	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index 376de4b..8eb3512 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,7 +40,7 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
-	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index df8c03b..ed79e39 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 
-	fbcs->csmr2 &= ~FBCS_CSMR_WP;
+	clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
 
 	/*
 	 * set up pin configuration - enabled 2nd output buffer's signals
 	 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
 	 * to use nCE signal
 	 */
-	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
-	gpio->pddr_timer |= 0x08;
-	gpio->ppd_timer |= 0x08;
-	gpio->pclrr_timer = 0;
-	gpio->podr_timer = 0;
+	clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+	setbits_8(&gpio->pddr_timer, 0x08);
+	setbits_8(&gpio->ppd_timer, 0x08);
+	out_8(&gpio->pclrr_timer, 0);
+	out_8(&gpio->podr_timer, 0);
 
 	nand->chip_delay = 60;
 	nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <spi.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,14 +52,14 @@ phys_size_t initdram(int board_type)
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
-	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
-	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+	if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+	    (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
 		return dramsize;
 
 	for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	udelay(200);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
 	__asm__("nop");
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
 
 	udelay(100);
 #endif
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 2a84514..0ca268e 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
 	 */
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
 #else
-	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
 	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
@@ -59,33 +60,34 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
-	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+	out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
 
-	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
-	sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+	out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
 
-	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+	out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	out_be32(&sdram->sdcr,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
 
 	udelay(100);
 #endif
@@ -105,26 +107,29 @@ int testdram(void)
 
 int ide_preinit(void)
 {
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
-	gpio->par_feci2c |=
-	    (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
-					   GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
-	gpio->par_ata |=
-	    (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
-	     GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
-	     | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
-	     GPIO_PAR_ATA_IORDY_IORDY);
-	gpio->par_pci |=
-	    (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	u32 tmp;
+
+	tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+	setbits_8(&gpio->par_fec, tmp);
+	tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+		(GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+	setbits_be16(&gpio->par_feci2c, tmp);
+
+	setbits_be16(&gpio->par_ata,
+		GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+		GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+		GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+		GPIO_PAR_ATA_IORDY_IORDY);
+	setbits_be16(&gpio->par_pci,
+		GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
 
 	return (0);
 }
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) MMAP_ATA;
+	atac_t *ata = (atac_t *) MMAP_ATA;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = {
@@ -136,24 +141,27 @@ void ide_set_reset(int idereset)
 	};			/* PIO 4 */
 
 	if (idereset) {
-		ata->cr = 0;	/* control reset */
+		/* control reset */
+		out_8(&ata->cr, 0);
 		udelay(10000);
 	} else {
 #define CALC_TIMING(t) (t + period - 1) / period
 		period = 1000000000 / gd->bus_clk;	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
-		ata->t1 = CALC_TIMING(piotms[2][0]);
-		ata->t2w = CALC_TIMING(piotms[2][1]);
-		ata->t2r = CALC_TIMING(piotms[2][1]);
-		ata->ta = CALC_TIMING(piotms[2][8]);
-		ata->trd = CALC_TIMING(piotms[2][7]);
-		ata->t4 = CALC_TIMING(piotms[2][3]);
-		ata->t9 = CALC_TIMING(piotms[2][6]);
-
-		ata->cr = 0x40;	/* IORDY enable */
+		out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+		out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+		out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+		out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+		out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+		out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+		/* IORDY enable */
+		out_8(&ata->cr, 0x40);
 		udelay(200000);
-		ata->cr |= 0x01;	/* IORDY enable */
+		/* IORDY enable */
+		setbits_8(&ata->cr, 0x01);
 	}
 }
 #endif
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 9f1ec38..fd9bddd 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,14 +41,14 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 #ifdef CONFIG_SYS_DRAMSZ1
 	u32 temp;
 #endif
 
-	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
 
 	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
 			break;
 	}
 	i--;
-	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
 
 #ifdef CONFIG_SYS_DRAMSZ1
 	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 	dramsize += temp;
-	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
 #endif
 
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
-	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 
 	udelay(100);
 
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index fbc0888..fb216d8 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <pci.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,14 +41,14 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
-	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
-	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+	siu_t *siu = (siu_t *) (MMAP_SIU);
+	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 #ifdef CONFIG_SYS_DRAMSZ1
 	u32 temp;
 #endif
 
-	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
 
 	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
 			break;
 	}
 	i--;
-	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
 
 #ifdef CONFIG_SYS_DRAMSZ1
 	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 	dramsize += temp;
-	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
 #endif
 
-	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
-	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
 
 	/* Issue PALL */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Issue LEMR */
-	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
-	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
-	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
 
-	sdram->mode = CONFIG_SYS_SDRAM_MODE;
+	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
 
-	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	out_be32(&sdram->ctrl,
+		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
 
 	udelay(100);
 
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 5c54357..7e3fa1a 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -24,18 +24,56 @@
 #include <common.h>
 #include <hwconfig.h>
 #include <i2c.h>
+#include <spi.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <pci.h>
 #include <mpc83xx.h>
 #include <vsc7385.h>
 #include <netdev.h>
+#include <fsl_esdhc.h>
 #include <asm/io.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_mpc83xx_serdes.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK	0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* active low */
+	clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+	/* inactive high */
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+	return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
 static u8 read_board_info(void)
 {
 	u8 val8;
@@ -109,6 +147,25 @@ void pci_init_board(void)
 */
 int misc_init_r(void)
 {
+#ifdef CONFIG_MPC8XXX_SPI
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+
+	/*
+	 * Set proper bits in SICRH to allow SPI on header J8
+	 *
+	 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+	 * switch. The pinmux configuration does not have a fine enough
+	 * granularity to support both simultaneously.
+	 */
+	clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+	puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+	/* Set header J8 SPI chip select output, disabled */
+	setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+	setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
 #ifdef CONFIG_VSC7385_IMAGE
 	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 		CONFIG_VSC7385_IMAGE_SIZE)) {
@@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 	fdt_fixup_dr_usb(blob, bd);
+	fdt_fixup_esdhc(blob, bd);
 }
 #endif
 
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index c75585e..a275d3a 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -87,10 +87,10 @@ local_bus_init(void)
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
 
 	} else {
 		/*
@@ -105,7 +105,7 @@ local_bus_init(void)
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
 		udelay(200);
 
 		/*
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 532d32a..13ca84b 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -269,13 +269,13 @@ local_bus_init(void)
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
 
 	} else {
-		lbc->lcrr &= (~0x80000000);	/* DLL Enabled */
+		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
 		udelay(200);
 
 		/*
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 3361614..4cfd61c 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -267,13 +267,13 @@ local_bus_init(void)
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr |= 0x80000000;	/* DLL Bypass */
+		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */
+		lbc->lcrr &= (~LCRR_DBYP);		/* DLL Enabled */
 
 	} else {
-		lbc->lcrr &= (~0x80000000);	/* DLL Enabled */
+		lbc->lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
 		udelay(200);
 
 		/*
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 1a165bf..285edbc 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -292,10 +292,10 @@ local_bus_init(void)
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
 
 	} else {
 		/*
@@ -310,7 +310,7 @@ local_bus_init(void)
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
 		udelay(200);
 
 		/*
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 10c5a42..6d00caf 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void)
 	cpu = gd->cpu;
 	/* P1014 and it's derivatives support max 16bit DDR width */
 	if (cpu->soc_ver == SVR_P1014) {
+		ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
 		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE;
-		ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1;
-		ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000;
-		ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000;
+		/* divide SA and EA by two and then mask the rest so we don't
+		 * write to reserved fields */
+		ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff;
 	}
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 7968919..0da8300 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -25,13 +25,11 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_NAND_SPL
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_VSC7385_ENET
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-#endif
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
 #ifdef CONFIG_SYS_NAND_BASE_PHYS
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p3060qds/Makefile b/board/freescale/p3060qds/Makefile
deleted file mode 100644
index ae136f4..0000000
--- a/board/freescale/p3060qds/Makefile
+++ /dev/null
@@ -1,54 +0,0 @@
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-y += ddr.o
-COBJS-y += eth.o
-COBJS-y += fixed_ddr.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-clean:
-	rm -f $(OBJS) $(SOBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/p3060qds/README b/board/freescale/p3060qds/README
deleted file mode 100644
index ec62798..0000000
--- a/board/freescale/p3060qds/README
+++ /dev/null
@@ -1,110 +0,0 @@
-Overview
-=========
-The P3060QDS is a Freescale reference board that hosts the six-core P3060 SOC.
-
-The P3060 Processor combines six e500mc Power Architecture processor
-cores(1.2GHz) with high-performance datapath acceleration
-architecture(DPAA), CoreNet fabric infrastructure, as well as network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and military/aerospace applications.
-
-
-P3060QDS Board Specifications:
-==============================
-Memory subsystem:
- * 2G Bytes UDIMM DDR3(64bit bus) with ECC on
- * 128M Bytes NOR flash single-chip memory
- * 16M Bytes SPI flash
- * 8K Bytes AT24C64 I2C EEPROM for RCW
-
-Ethernet(Default SERDES 0x19):
- * FM1-dTSEC1: connected to RGMII PHY1 (Vitesse VSC8641 on board,Bottom of dual RJ45)
- * FM1-dTSEC2: connected to RGMII PHY2 (Vitesse VSC8641 on board,Top of dual RJ45)
- * FM1-dTSEC3: connected to SGMII PHY  (Vitesse VSC8234 port1 in slot1)
- * FM1-dTSEC4: connected to SGMII PHY  (Vitesse VSC8234 port3 in slot1)
- * FM2-dTSEC1: connected to SGMII PHY  (Vitesse VSC8234 port0 in slot2)
- * FM2-dTSEC2: connected to SGMII PHY  (Vitesse VSC8234 port2 in slot2)
- * FM2-dTSEC3: connected to SGMII PHY  (Vitesse VSC8234 port0 in slot1)
- * FM2-dTSEC4: connected to SGMII PHY  (Vitesse VSC8234 port2 in slot1)
-
-PCIe:
- * PCIe1: Lanes A, B, C and D of Bank1 are connected to one x4 PCIe SLOT4
- * PCIe2: Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT3
-
-RapidIO:
- * sRIO1: Lanes E, F, G and H of Bank1 are connected to sRIO1 (SLOT3)
- * sRIO2: Lanes A, B, C and D of Bank1 are connected to sRIO2 (SLOT4)
-
-USB:
- * USB1: connected via an external ULPI PHY SMC3315 to a TYPE-A interface
- * USB2: connected via an external ULPI PHY SMC3315 to a TYPE-AB interface
-
-I2C:
- * I2C1_CH0: EEPROM AT24C64(0x50) RCW, AT24C02(0x51) DDR SPD,
-	     AT24C02(0x53) DDR SPD, AT24C02(0x57) SystemID, RTC DS3232(0x68)
- * I2C1_CH1: 1588 RiserCard(0x55), HSLB Testport, TempMon
-	     ADT7461(0x4C), SerDesMux DS64MB201(0x51/59/5C/5D)
- * I2C1_CH2: VDD/GVDD/GIDD ZL6100 (0x21/0x22/0x23/0x24/0x40)
- * I2C1_CH3: OCM CFG AT24C02(0x55), OCM IPL AT24C64(0x56)
- * I2C1_CH4: PCIe SLOT1
- * I2C1_CH5: PCIe SLOT2
- * I2C1_CH6: PCIe SLOT3
- * I2C1_CH7: PCIe SLOT4
- * I2C2: NULL
- * I2C3: NULL
-
-UART:
- * Supports two UARTs up to 115200 bps for console
-
-
-Boot from NOR flash
-===================
-1. Build image
-	export ARCH=powerpc
-	export CROSS_COMPILE=/your_path/gcc-4.5.xx-eglibc-2.11.xx/powerpc-linux-gnu/bin/powerpc-linux-gnu-
-	make P3060QDS_config
-	make
-
-2. Program image
-	=> tftp 1000000 u-boot.bin
-	=> protect off all
-	=> erase eff80000 efffffff
-	=> cp.b 1000000 eff80000 80000
-
-3. Program RCW
-	=> tftp 1000000 rcw.bin
-	=> protect off all
-	=> erase e8000000 e801ffff
-	=> cp.b 1000000 e8000000 50
-
-4. Program FMAN Firmware ucode
-	=> tftp 1000000 ucode.bin
-	=> protect off all
-	=> erase ef000000 ef0fffff
-	=> cp.b 1000000 ef000000 2000
-
-5. Change DIP-switch
-	RCW Location: SW1[1-5] = 01101 (eLBC 16bit NOR flash)
-	Note: 1 stands for 'on', 0 stands for 'off'
-
-
-Using the Device Tree Source File
-=================================
-To create the DTB (Device Tree Binary) image file, use a command
-similar to this:
-	dtc -O dtb -b 0 -p 1024 p3060qds.dts > p3060qds.dtb
-
-Or use the following command:
-	{linux-2.6}/make p3060qds.dtb ARCH=powerpc
-
-then the dtb file will be generated under the following directory:
-	{linux-2.6}/arch/powerpc/boot/p3060qds.dtb
-
-
-Booting Linux
-=============
-Place a linux uImage in the TFTP disk area.
-	tftp 1000000 uImage
-	tftp 2000000 rootfs.ext2.gz.uboot
-	tftp 3000000 p3060rdb.dtb
-	bootm 1000000 2000000 3000000
diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c
deleted file mode 100644
index 9affbf0..0000000
--- a/board/freescale/p3060qds/ddr.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <hwconfig.h>
-#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-#include <asm/fsl_law.h>
-
-#include "p3060qds.h"
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
-	int i;
-	char buf[32];
-	fsl_ddr_cfg_regs_t ddr_cfg_regs;
-	phys_size_t ddr_size;
-	unsigned int lawbar1_target_id;
-	ulong ddr_freq, ddr_freq_mhz;
-
-	ddr_freq = get_ddr_freq(0);
-	ddr_freq_mhz = ddr_freq / 1000000;
-
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
-
-	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
-		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
-		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
-			memcpy(&ddr_cfg_regs,
-				fixed_ddr_parm_0[i].ddr_settings,
-				sizeof(ddr_cfg_regs));
-			break;
-		}
-	}
-
-	if (fixed_ddr_parm_0[i].max_freq == 0)
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-			strmhz(buf, ddr_freq));
-
-	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
-
-	/*
-	 * setup laws for DDR. If not interleaving, presuming half memory on
-	 * DDR1 and the other half on DDR2
-	 */
-	if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
-		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
-				 ddr_size,
-				 LAW_TRGT_IF_DDR_INTRLV) < 0) {
-			printf("ERROR setting Local Access Windows for DDR\n");
-			return 0;
-		}
-	} else {
-		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
-		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
-				 ddr_size,
-				 lawbar1_target_id) < 0) {
-			printf("ERROR setting Local Access Windows for DDR\n");
-			return 0;
-		}
-	}
-	return ddr_size;
-}
-
-struct board_specific_params {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_params udimm[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |      |delay |
-	 */
-	{4,   850,    4,     6,   0xff,    2,  0},
-	{4,   950,    5,     7,   0xff,    2,  0},
-	{4,  1050,    5,     8,   0xff,    2,  0},
-	{4,  1250,    5,    10,   0xff,    2,  0},
-	{4,  1350,    5,    11,   0xff,    2,  0},
-	{4,  1666,    5,    12,   0xff,    2,  0},
-	{2,   850,    5,     6,   0xff,    2,  0},
-	{2,   950,    5,     7,   0xff,    2,  0},
-	{2,  1250,    4,     6,   0xff,    2,  0},
-	{2,  1350,    5,     7,   0xff,    2,  0},
-	{2,  1666,    5,     8,   0xff,    2,  0},
-	{1,   850,    4,     5,   0xff,    2,  0},
-	{1,   950,    4,     7,   0xff,    2,  0},
-	{1,  1666,    4,     8,   0xff,    2,  0},
-	{}
-};
-
-static const struct board_specific_params rdimm[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi|  clk| wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz|adjst| start |      |delay |
-	 */
-	{4,   850,    4,     6,   0xff,    2,  0},
-	{4,   950,    5,     7,   0xff,    2,  0},
-	{4,  1050,    5,     8,   0xff,    2,  0},
-	{4,  1250,    5,    10,   0xff,    2,  0},
-	{4,  1350,    5,    11,   0xff,    2,  0},
-	{4,  1666,    5,    12,   0xff,    2,  0},
-	{2,   850,    4,     6,   0xff,    2,  0},
-	{2,  1050,    4,     7,   0xff,    2,  0},
-	{2,  1666,    4,     8,   0xff,    2,  0},
-	{1,   850,    4,     5,   0xff,    2,  0},
-	{1,   950,    4,     7,   0xff,    2,  0},
-	{1,  1666,    4,     8,   0xff,    2,  0},
-	{}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	const struct board_specific_params *pbsp, *pbsp_highest = NULL;
-	ulong ddr_freq;
-
-	if (ctrl_num) {
-		printf("Wrong parameter for controller number %d", ctrl_num);
-		return;
-	}
-	if (!pdimm->n_ranks)
-		return;
-
-	if (popts->registered_dimm_en)
-		pbsp = rdimm;
-	else
-		pbsp = udimm;
-
-	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
-	 * freqency and n_banks specified in board_specific_parameters table.
-	 */
-	ddr_freq = get_ddr_freq(0) / 1000000;
-	while (pbsp->datarate_mhz_high) {
-		if (pbsp->n_ranks == pdimm->n_ranks) {
-			if (ddr_freq <= pbsp->datarate_mhz_high) {
-				popts->cpo_override = pbsp->cpo;
-				popts->write_data_delay =
-					pbsp->write_data_delay;
-				popts->clk_adjust = pbsp->clk_adjust;
-				popts->wrlvl_start = pbsp->wrlvl_start;
-				popts->twoT_en = pbsp->force_2T;
-				goto found;
-			}
-			pbsp_highest = pbsp;
-		}
-		pbsp++;
-	}
-
-	if (pbsp_highest) {
-		printf("Error: board specific timing not found "
-			"for data rate %lu MT/s!\n"
-			"Trying to use the highest speed (%u) parameters\n",
-			ddr_freq, pbsp_highest->datarate_mhz_high);
-		popts->cpo_override = pbsp_highest->cpo;
-		popts->write_data_delay = pbsp_highest->write_data_delay;
-		popts->clk_adjust = pbsp_highest->clk_adjust;
-		popts->wrlvl_start = pbsp_highest->wrlvl_start;
-		popts->twoT_en = pbsp_highest->force_2T;
-	} else {
-		panic("DIMM is not supported by this board");
-	}
-
-
-found:
-
-	/*
-	 * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
-	 * However SPD still claims CL=7 is supported. Extensive tests
-	 * confirmed this board cannot work stably with CL=7 with this
-	 * particular DIMM.
-	 */
-	if (ddr_freq >= 800 && ddr_freq < 1066 && \
-		!strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
-		popts->cas_latency_override = 1;
-		popts->cas_latency_override_value = 8;
-		debug("Override CL to 8\n");
-	}
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-	/*
-	 * Write leveling override
-	 */
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-
-	/*
-	 * Rtt and Rtt_WR override
-	 */
-	popts->rtt_override = 0;
-
-	/* Enable ZQ calibration */
-	popts->zq_en = 1;
-
-	/* DHC_EN =1, ODT = 60 Ohm */
-	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
-}
-
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size;
-
-	puts("Initializing....");
-
-	if (fsl_use_spd()) {
-		puts("using SPD\n");
-		dram_size = fsl_ddr_sdram();
-	} else {
-		puts("using fixed parameters\n");
-		dram_size = fixed_sdram();
-	}
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
-	debug("    DDR: ");
-	return dram_size;
-}
diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c
deleted file mode 100644
index 3f812db..0000000
--- a/board/freescale/p3060qds/eth.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <malloc.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <asm/fsl_dtsec.h>
-
-#include "../common/qixis.h"
-#include "../common/fman.h"
-
-#include "p3060qds_qixis.h"
-
-#define EMI_NONE       0xffffffff
-#define EMI1_RGMII1    0
-#define EMI1_SLOT1     1
-#define EMI1_SLOT2     2
-#define EMI1_SLOT3     3
-#define EMI1_RGMII2    4
-
-static int mdio_mux[NUM_FM_PORTS];
-
-static char *mdio_names[5] = {
-	"P3060QDS_MDIO0",
-	"P3060QDS_MDIO1",
-	"P3060QDS_MDIO2",
-	"P3060QDS_MDIO3",
-	"P3060QDS_MDIO4",
-};
-
-/*
- * Mapping of all 18 SERDES lanes to board slots.
- * A value of '0' here means that the mapping must be determined
- * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
- */
-static u8 lane_to_slot[] = {
-	4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
-};
-
-static char *p3060qds_mdio_name_for_muxval(u32 muxval)
-{
-	return mdio_names[muxval];
-}
-
-struct mii_dev *mii_dev_for_muxval(u32 muxval)
-{
-	struct mii_dev *bus;
-	char *name = p3060qds_mdio_name_for_muxval(muxval);
-
-	if (!name) {
-		printf("No bus for muxval %x\n", muxval);
-		return NULL;
-	}
-
-	bus = miiphy_get_dev_by_name(name);
-
-	if (!bus) {
-		printf("No bus by name %s\n", name);
-		return NULL;
-	}
-
-	return bus;
-}
-
-struct p3060qds_mdio {
-	u32 muxval;
-	struct mii_dev *realbus;
-};
-
-static void p3060qds_mux_mdio(u32 muxval)
-{
-	u8 brdcfg4;
-
-	brdcfg4 = QIXIS_READ(brdcfg[4]);
-	brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
-	brdcfg4 |= (muxval << 4);
-	QIXIS_WRITE(brdcfg[4], brdcfg4);
-}
-
-static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
-				int regnum)
-{
-	struct p3060qds_mdio *priv = bus->priv;
-
-	p3060qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->read(priv->realbus, addr, devad, regnum);
-}
-
-static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
-				int regnum, u16 value)
-{
-	struct p3060qds_mdio *priv = bus->priv;
-
-	p3060qds_mux_mdio(priv->muxval);
-
-	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
-}
-
-static int p3060qds_mdio_reset(struct mii_dev *bus)
-{
-	struct p3060qds_mdio *priv = bus->priv;
-
-	return priv->realbus->reset(priv->realbus);
-}
-
-static int p3060qds_mdio_init(char *realbusname, u32 muxval)
-{
-	struct p3060qds_mdio *pmdio;
-	struct mii_dev *bus = mdio_alloc();
-
-	if (!bus) {
-		printf("Failed to allocate P3060QDS MDIO bus\n");
-		return -1;
-	}
-
-	pmdio = malloc(sizeof(*pmdio));
-	if (!pmdio) {
-		printf("Failed to allocate P3060QDS private data\n");
-		free(bus);
-		return -1;
-	}
-
-	bus->read = p3060qds_mdio_read;
-	bus->write = p3060qds_mdio_write;
-	bus->reset = p3060qds_mdio_reset;
-	sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
-
-	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
-
-	if (!pmdio->realbus) {
-		printf("No bus with name %s\n", realbusname);
-		free(bus);
-		free(pmdio);
-		return -1;
-	}
-
-	pmdio->muxval = muxval;
-	bus->priv = pmdio;
-
-	return mdio_register(bus);
-}
-
-void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
-				enum fm_port port, int offset)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
-			  FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
-	if (mdio_mux[port] == EMI1_RGMII1)
-		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
-
-	if (mdio_mux[port] == EMI1_RGMII2)
-		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
-
-	if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
-		|| (srds_prtcl == 0x6))) {
-		switch (port) {
-		case FM2_DTSEC4:
-			fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
-			break;
-		case FM1_DTSEC4:
-			fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
-			break;
-		default:
-			break;
-		}
-	}
-
-	if (mdio_mux[port] == EMI1_SLOT3) {
-		switch (port) {
-		case FM2_DTSEC3:
-			fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
-			break;
-		case FM1_DTSEC3:
-			fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
-			break;
-		default:
-			break;
-		}
-	}
-}
-
-void fdt_fixup_board_enet(void *fdt)
-{
-	int i, lane, idx;
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		idx = i - FM1_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-
-			switch (mdio_mux[i]) {
-			case EMI1_SLOT1:
-				if (lane >= 14) {
-					fdt_status_okay_by_alias(fdt,
-						"emi1_slot1");
-					fdt_status_disabled_by_alias(fdt,
-						"emi1_slot1_bk1");
-				} else {
-					fdt_status_disabled_by_alias(fdt,
-						"emi1_slot1");
-					fdt_status_okay_by_alias(fdt,
-						"emi1_slot1_bk1");
-				}
-				break;
-			case EMI1_SLOT2:
-				fdt_status_okay_by_alias(fdt, "emi1_slot2");
-				break;
-			case EMI1_SLOT3:
-				fdt_status_okay_by_alias(fdt, "emi1_slot3");
-				break;
-			}
-		break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC1)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
-
-			if (i == FM1_DTSEC2)
-				fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
-			break;
-		default:
-			break;
-		}
-	}
-#if (CONFIG_SYS_NUM_FMAN == 2)
-	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
-		idx = i - FM2_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
-			if (lane >= 0) {
-				switch (mdio_mux[i]) {
-				case EMI1_SLOT1:
-					if (lane >= 14)
-						fdt_status_okay_by_alias(fdt,
-							"emi1_slot1");
-					else
-						fdt_status_okay_by_alias(fdt,
-							"emi1_slot1_bk1");
-					break;
-				case EMI1_SLOT2:
-					fdt_status_okay_by_alias(fdt,
-						"emi1_slot2");
-					break;
-				case EMI1_SLOT3:
-					fdt_status_okay_by_alias(fdt,
-						"emi1_slot3");
-					break;
-				}
-			}
-			break;
-		default:
-			break;
-		}
-	}
-#endif
-}
-
-static void initialize_lane_to_slot(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int sdprtl = (in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
-	switch (sdprtl) {
-	case 0x03:
-	case 0x06:
-		lane_to_slot[8] = 1;
-		lane_to_slot[9] = lane_to_slot[8];
-		lane_to_slot[16] = 5;
-		lane_to_slot[17] = lane_to_slot[16];
-		break;
-	case 0x16:
-	case 0x19:
-	case 0x1C:
-		lane_to_slot[8] = 5;
-		lane_to_slot[9] = lane_to_slot[8];
-		lane_to_slot[16] = 1;
-		lane_to_slot[17] = lane_to_slot[16];
-		break;
-	default:
-		puts("Invalid SerDes protocol for P3060QDS\n");
-		break;
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_FMAN_ENET
-	struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
-	int i;
-	struct fsl_pq_mdio_info dtsec_mdio_info;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int srds_cfg = (in_be32(&gur->rcwsr[4]) &
-				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
-	initialize_lane_to_slot();
-
-	/*
-	 * Set TBIPA on FM1@DTSEC1.  This is needed for configurations
-	 * where FM1@DTSEC1 isn't used directly, since it provides
-	 * MDIO for other ports.
-	 */
-	out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
-	/* Initialize the mdio_mux array so we can recognize empty elements */
-	for (i = 0; i < NUM_FM_PORTS; i++)
-		mdio_mux[i] = EMI_NONE;
-
-	dtsec_mdio_info.regs =
-		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
-	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
-
-	/* Register the 1G MDIO bus */
-	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
-
-	/* Register the 5 muxing front-ends to the MDIO buses */
-	if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
-		p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
-
-	if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
-		p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
-	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
-	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
-	p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-
-	if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
-		fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
-	else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
-
-	if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
-		fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
-	else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
-
-	fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-	fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
-
-	switch (srds_cfg) {
-	case 0x03:
-	case 0x06:
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
-		break;
-	case 0x16:
-	case 0x19:
-	case 0x1C:
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
-		break;
-	default:
-		puts("Invalid SerDes protocol for P3060QDS\n");
-		break;
-	}
-
-	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1, lane, slot;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			if (QIXIS_READ(present) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			};
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-			if (i == FM1_DTSEC1) {
-				mdio_mux[i] = EMI1_RGMII1;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-			} else if (i == FM1_DTSEC2) {
-				mdio_mux[i] = EMI1_RGMII2;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-			}
-			break;
-		default:
-			break;
-		}
-	}
-
-#if (CONFIG_SYS_NUM_FMAN == 2)
-	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
-		int idx = i - FM2_DTSEC1, lane, slot;
-		switch (fm_info_get_enet_if(i)) {
-		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot[lane];
-			if (QIXIS_READ(present) & (1 << (slot - 1)))
-				fm_disable_port(i);
-			switch (slot) {
-			case 1:
-				mdio_mux[i] = EMI1_SLOT1;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 2:
-				mdio_mux[i] = EMI1_SLOT2;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			case 3:
-				mdio_mux[i] = EMI1_SLOT3;
-				fm_info_set_mdio(i,
-					mii_dev_for_muxval(mdio_mux[i]));
-				break;
-			};
-			break;
-		default:
-			break;
-		}
-	}
-#endif /* CONFIG_SYS_NUM_FMAN */
-
-	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
-
-	return pci_eth_init(bis);
-}
diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c
deleted file mode 100644
index 125988d..0000000
--- a/board/freescale/p3060qds/fixed_ddr.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-
-#define CONFIG_SYS_DDR_TIMING_3_1200	0x01030000
-#define CONFIG_SYS_DDR_TIMING_0_1200	0xCC550104
-#define CONFIG_SYS_DDR_TIMING_1_1200	0x868FAA45
-#define CONFIG_SYS_DDR_TIMING_2_1200	0x0FB8A912
-#define CONFIG_SYS_DDR_MODE_1_1200	0x00441A40
-#define CONFIG_SYS_DDR_MODE_2_1200	0x00100000
-#define CONFIG_SYS_DDR_INTERVAL_1200	0x12480100
-#define CONFIG_SYS_DDR_CLK_CTRL_1200	0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_1000	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_1000	0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_1000	0x727DF944
-#define CONFIG_SYS_DDR_TIMING_2_1000	0x0FB088CF
-#define CONFIG_SYS_DDR_MODE_1_1000	0x00441830
-#define CONFIG_SYS_DDR_MODE_2_1000	0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_1000	0x0F3C0100
-#define CONFIG_SYS_DDR_CLK_CTRL_1000	0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_900	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_900	0xCC440104
-#define CONFIG_SYS_DDR_TIMING_1_900	0x616ba844
-#define CONFIG_SYS_DDR_TIMING_2_900	0x0fb088ce
-#define CONFIG_SYS_DDR_MODE_1_900	0x00441620
-#define CONFIG_SYS_DDR_MODE_2_900	0x00080000
-#define CONFIG_SYS_DDR_INTERVAL_900	0x0db60100
-#define CONFIG_SYS_DDR_CLK_CTRL_900	0x02800000
-
-#define CONFIG_SYS_DDR_TIMING_3_800	0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_800	0xcc330104
-#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b4744
-#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa888cc
-#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
-#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
-#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x000000FF
-#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS		0x000000FF
-#define CONFIG_SYS_DDR_CS3_BNDS		0x000000FF
-#define CONFIG_SYS_DDR2_CS0_BNDS	0x000000FF
-#define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
-#define CONFIG_SYS_DDR2_CS2_BNDS	0x000000FF
-#define CONFIG_SYS_DDR2_CS3_BNDS	0x000000FF
-#define CONFIG_SYS_DDR_CS0_CONFIG	0xA0044202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
-#define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
-#define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
-#define CONFIG_SYS_DDR2_CS0_CONFIG	0x80044202
-#define CONFIG_SYS_DDR2_CS1_CONFIG	0x80004202
-#define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
-#define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG	0x80004202
-#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_TIMING_4		0x00000001
-#define CONFIG_SYS_DDR_TIMING_5		0x02401400
-#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
-#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F607
-#define CONFIG_SYS_DDR_SDRAM_CFG	0xE7044000
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x24401031
-#define CONFIG_SYS_DDR_RCW_1		0x00000000
-#define CONFIG_SYS_DDR_RCW_2		0x00000000
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
-	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
-	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
-	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
-	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
-	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
-	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
-	.cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
-	.cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
-	.cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
-	.cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{750, 850, &ddr_cfg_regs_800},
-	{850, 950, &ddr_cfg_regs_900},
-	{950, 1050, &ddr_cfg_regs_1000},
-	{1050, 1250, &ddr_cfg_regs_1200},
-	{0, 0, NULL}
-};
diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c
deleted file mode 100644
index 43e7f28..0000000
--- a/board/freescale/p3060qds/p3060qds.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <linux/compiler.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-#include <fm_eth.h>
-#include <configs/P3060QDS.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-#include "../common/qixis.h"
-#include "p3060qds.h"
-#include "p3060qds_qixis.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	u8 sw;
-	struct cpu_type *cpu = gd->cpu;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-	unsigned int i;
-
-	printf("Board: %s", cpu->name);
-	puts("QDS, ");
-
-	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
-
-	sw = QIXIS_READ(brdcfg[0]);
-	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
-
-	if (sw < 0x8)
-		printf("vBank: %d\n", sw);
-	else if (sw == 0x8)
-		puts("Promjet\n");
-	else if (sw == 0x9)
-		puts("NAND\n");
-	else
-		printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
-
-	puts("Reset Configuration Word (RCW):");
-	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
-		u32 rcw = in_be32(&gur->rcwsr[i]);
-
-		if ((i % 4) == 0)
-			printf("\n       %08x:", i * 4);
-		printf(" %08x", rcw);
-	}
-	puts("\n");
-
-	puts("SERDES Reference Clocks: ");
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < 3; i++) {
-		static const char * const freq[] = {"100", "125", "Reserved",
-						"156.25"};
-		unsigned int clock = (sw >> (2 * i)) & 3;
-
-		printf("Bank%u=%sMhz ", i+1, freq[clock]);
-	}
-	puts("\n");
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
-	/* only single DDR controller on QDS board, disable DDR1_MCK4/5 */
-	setbits_be32(&gur->ddrclkdr, 0x00030000);
-
-	return 0;
-}
-
-void board_config_serdes_mux(void)
-{
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int cfg = (in_be32(&gur->rcwsr[4]) &
-			FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
-
-	switch (cfg) {
-	case 0x03:
-	case 0x06:
-		/* set Lane I,J as SGMII */
-		QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A |
-				       BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A);
-		break;
-	case 0x16:
-	case 0x19:
-	case 0x1c:
-		/* set Lane I,J as Aurora Debug */
-		QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B |
-				       BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B);
-		break;
-	default:
-		puts("Invalid SerDes protocol for P3060QDS\n");
-		break;
-	}
-}
-
-void board_config_usb_mux(void)
-{
-	u8 brdcfg4, brdcfg5, brdcfg7;
-	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
-	u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1;
-	u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2;
-
-	brdcfg4 = QIXIS_READ(brdcfg[4]);
-	brdcfg4 &= ~BRDCFG4_EC_MODE_MASK;
-	if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
-		 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
-		brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB;
-
-	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) &&
-		 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
-		 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
-		brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB;
-
-	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
-		 (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) {
-		brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII;
-
-	} else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) &&
-		 ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) ||
-		 (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) {
-		brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII;
-	} else {
-		brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII;
-	}
-	QIXIS_WRITE(brdcfg[4], brdcfg4);
-
-	brdcfg5 = QIXIS_READ(brdcfg[5]);
-	brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK);
-	brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL);
-	QIXIS_WRITE(brdcfg[5], brdcfg5);
-
-	brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT |
-		BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1;
-	QIXIS_WRITE(brdcfg[7], brdcfg7);
-}
-
-int board_early_init_r(void)
-{
-	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
-
-	/*
-	 * Remap Boot flash + PROMJET region to caching-inhibited
-	 * so that flash can be erased properly.
-	 */
-
-	/* Flush d-cache and invalidate i-cache of any FLASH data */
-	flush_dcache();
-	invalidate_icache();
-
-	/* invalidate existing TLB entry for flash + promjet */
-	disable_tlb(flash_esel);
-
-	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
-	set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
-#endif
-	board_config_serdes_mux();
-	board_config_usb_mux();
-
-	return 0;
-}
-
-static const char *serdes_clock_to_string(u32 clock)
-{
-	switch (clock) {
-	case SRDS_PLLCR0_RFCK_SEL_100:
-		return "100";
-	case SRDS_PLLCR0_RFCK_SEL_125:
-		return "125";
-	case SRDS_PLLCR0_RFCK_SEL_156_25:
-		return "156.25";
-	default:
-		return "150";
-	}
-}
-
-#define NUM_SRDS_BANKS	3
-
-int misc_init_r(void)
-{
-	serdes_corenet_t *srds_regs;
-	u32 actual[NUM_SRDS_BANKS];
-	unsigned int i;
-	u8 sw;
-
-	sw = QIXIS_READ(brdcfg[2]);
-	for (i = 0; i < 3; i++) {
-		unsigned int clock = (sw >> (2 * i)) & 3;
-		switch (clock) {
-		case 0:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
-			break;
-		case 1:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
-			break;
-		case 3:
-			actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
-			break;
-		default:
-			printf("Warning: SDREFCLK%u switch setting of '10' is "
-				"unsupported\n", i + 1);
-			break;
-		}
-	}
-
-	srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
-	for (i = 0; i < NUM_SRDS_BANKS; i++) {
-		u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0);
-		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
-		if (expected != actual[i]) {
-			printf("Warning: SERDES bank %u expects reference clock"
-			       " %sMHz, but actual is %sMHz\n", i + 1,
-			       serdes_clock_to_string(expected),
-			       serdes_clock_to_string(actual[i]));
-		}
-	}
-
-	return 0;
-}
-
-/*
- * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v,
- * 18 means CVDD is 1.8v.
- */
-static u8 IO_VSEL[] = {
-	33, 33, 33, 25, 25, 25, 18, 18, 18,
-	33, 33, 33, 25, 25, 25, 18, 18, 18,
-	33, 33, 33, 25, 25, 25, 18, 18, 18,
-	33, 33, 33, 33, 33
-};
-
-#define IO_VSEL_MASK	0x1f
-
-/*
- * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD,
- * then set status of  spi flash nodes to 'disabled' according to CVDD.
- * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi
- * flash2, CVDD '18' will select spi flash3.
- */
-void fdt_fixup_board_spi(void *blob)
-{
-	u8 sw5 = QIXIS_READ(dutcfg[3]);
-
-	switch (IO_VSEL[sw5 & IO_VSEL_MASK]) {
-	/* 3.3v */
-	case 33:
-		do_fixup_by_compat(blob, "atmel,at45db081d", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		break;
-	/* 2.5v */
-	case 25:
-		do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		do_fixup_by_compat(blob, "spansion,en25q32", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		do_fixup_by_compat(blob, "spansion,sst25wf040", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		break;
-	/* 1.8v */
-	case 18:
-		do_fixup_by_compat(blob, "spansion,s25sl12801", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		do_fixup_by_compat(blob, "spansion,en25q32", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		do_fixup_by_compat(blob, "atmel,at45db081d", "status",
-				"disabled", strlen("disabled") + 1, 1);
-		break;
-	}
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = getenv_bootm_low();
-	size = getenv_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-	fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#ifdef CONFIG_PCI
-	pci_of_setup(blob, bd);
-#endif
-
-	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
-	fdt_fixup_board_spi(blob);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-	fdt_fixup_fman_ethernet(blob);
-	fdt_fixup_board_enet(blob);
-#endif
-}
diff --git a/board/freescale/p3060qds/p3060qds.h b/board/freescale/p3060qds/p3060qds.h
deleted file mode 100644
index 3da6815..0000000
--- a/board/freescale/p3060qds/p3060qds.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __P3060QDS_H__
-#define __P3060QDS_H__
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/u-boot.h>
-
-void fdt_fixup_board_enet(void *blob);
-void pci_of_setup(void *blob, bd_t *bd);
-extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-
-#endif
diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h
deleted file mode 100644
index 4d5d6a2..0000000
--- a/board/freescale/p3060qds/p3060qds_qixis.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __P3060QDS_QIXIS_H__
-#define __P3060QDS_QIXIS_H__
-
-/* Definitions of QIXIS Registers for P3060QDS */
-
-/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
-#define BRDCFG4_EC_MODE_MASK		0x0F
-#define BRDCFG4_EC2_MII_EC1_MII	0x00
-#define BRDCFG4_EC2_MII_EC1_USB	0x03
-#define BRDCFG4_EC2_USB_EC1_MII	0x0C
-#define BRDCFG4_EC2_USB_EC1_USB	0x0F
-#define BRDCFG4_EC2_USB_EC1_RGMII	0x0E
-#define BRDCFG4_EC2_RGMII_EC1_USB	0x0B
-#define BRDCFG4_EC2_RGMII_EC1_RGMII	0x0A
-#define BRDCFG4_EMISEL_MASK		0xF0
-
-#define BRDCFG5_ECLKS_MASK		0x80
-#define BRDCFG5_USB1ID_MASK		0x40
-#define BRDCFG5_USB2ID_MASK		0x20
-#define BRDCFG5_GC2MX_MASK		0x0C
-#define BRDCFG5_T15MX_MASK		0x03
-#define BRDCFG5_ECLKS_IEEE1588_CM	0x80
-#define BRDCFG5_USB1ID_CTRL		0x40
-#define BRDCFG5_USB2ID_CTRL		0x20
-
-#define BRDCFG6_SD1MX_A		0x01
-#define BRDCFG6_SD1MX_B		0x00
-#define BRDCFG6_SD2MX_A		0x02
-#define BRDCFG6_SD2MX_B		0x00
-#define BRDCFG6_SD3MX_A		0x04
-#define BRDCFG6_SD3MX_B		0x00
-#define BRDCFG6_SD4MX_A		0x08
-#define BRDCFG6_SD4MX_B		0x00
-
-#define BRDCFG7_JTAGMX_MASK		0xC0
-#define BRDCFG7_IQ1MX_MASK		0x20
-#define BRDCFG7_G1MX_MASK		0x10
-#define BRDCFG7_D1MX_MASK		0x0C
-#define BRDCFG7_I3MX_MASK		0x03
-#define BRDCFG7_JTAGMX_AURORA		0x00
-#define BRDCFG7_JTAGMX_FPGA		0x80
-#define BRDCFG7_JTAGMX_COP_JTAG	0xC0
-#define BRDCFG7_IQ1MX_IRQ_EVT		0x00
-#define BRDCFG7_IQ1MX_USB2		0x20
-#define BRDCFG7_G1MX_USB1		0x00
-#define BRDCFG7_G1MX_TSEC3		0x10
-#define BRDCFG7_D1MX_DMA		0x00
-#define BRDCFG7_D1MX_TSEC3USB		0x04
-#define BRDCFG7_D1MX_HDLC2		0x08
-#define BRDCFG7_I3MX_UART2_I2C34	0x00
-#define BRDCFG7_I3MX_GPIO_EVT		0x01
-#define BRDCFG7_I3MX_USB1		0x02
-#define BRDCFG7_I3MX_TSEC3		0x03
-
-#endif