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authorShaohui Xie <Shaohui.Xie@freescale.com>2013-09-11 12:58:34 +0800
committerYork Sun <yorksun@freescale.com>2013-10-16 16:13:12 -0700
commitef9a1f9a4f9576f345308351c707b3ce85d0451f (patch)
treede2332ce52d4472d14ba565ea5c0f53c98c9323f /board/freescale
parent55964bb6a21a1c68791f9757fe8353b53c0f9c3d (diff)
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powerpc/t4240: updated rcw_cfg to align with default hardware configuration
Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/t4qds/t4_rcw.cfg8
1 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 6ac95ff..74df01a 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol 1_28_6_12
-14180019 0c101916 00000000 00000000
-04383060 30548c00 6c020000 19000000
-00000000 ee0000ee 00000000 000187fc
-00000000 00000000 00000000 00000018
+120c0019 0c101915 00000000 00000000
+04383063 30548c00 6c020000 1d000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000020