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authorStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
committerStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
commite72d344386bf80738fab7a6bd37cb321f443093a (patch)
treed3e02055e6aa903ab80ef87c78d2f38e93981dcf /board/freescale
parent258c98f8d36ef35d7cb7604847ba73e64d702c2a (diff)
parentbd2a4888b123713adec271d6c8040ca9f609aa2f (diff)
downloadu-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.zip
u-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.tar.gz
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Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/c29xpcie/MAINTAINERS2
-rw-r--r--board/freescale/common/pq-mds-pib.c2
-rw-r--r--board/freescale/corenet_ds/MAINTAINERS1
-rw-r--r--board/freescale/ls1021aqds/MAINTAINERS1
-rw-r--r--board/freescale/ls1021aqds/Makefile1
-rw-r--r--board/freescale/ls1021aqds/dcu.c92
-rw-r--r--board/freescale/ls1021aqds/ddr.c17
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c89
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds_qixis.h2
-rw-r--r--board/freescale/ls1021atwr/MAINTAINERS1
-rw-r--r--board/freescale/ls1021atwr/ls1021atwr.c28
-rw-r--r--board/freescale/mpc8360emds/Kconfig12
-rw-r--r--board/freescale/mpc8360emds/MAINTAINERS15
-rw-r--r--board/freescale/mpc8360emds/Makefile9
-rw-r--r--board/freescale/mpc8360emds/README155
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c453
-rw-r--r--board/freescale/mpc8360emds/pci.c147
-rw-r--r--board/freescale/mpc8360erdk/Kconfig12
-rw-r--r--board/freescale/mpc8360erdk/MAINTAINERS7
-rw-r--r--board/freescale/mpc8360erdk/Makefile9
-rw-r--r--board/freescale/mpc8360erdk/mpc8360erdk.c350
-rw-r--r--board/freescale/mpc8360erdk/nand.c89
-rw-r--r--board/freescale/mpc837xerdb/MAINTAINERS4
-rw-r--r--board/freescale/p1_p2_rdb/Kconfig12
-rw-r--r--board/freescale/p1_p2_rdb/MAINTAINERS37
-rw-r--r--board/freescale/p1_p2_rdb/Makefile30
-rw-r--r--board/freescale/p1_p2_rdb/README145
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c221
-rw-r--r--board/freescale/p1_p2_rdb/law.c17
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c303
-rw-r--r--board/freescale/p1_p2_rdb/pci.c27
-rw-r--r--board/freescale/p1_p2_rdb/spl.c141
-rw-r--r--board/freescale/p1_p2_rdb/spl_minimal.c84
-rw-r--r--board/freescale/p1_p2_rdb/tlb.c91
-rw-r--r--board/freescale/p2020come/Kconfig12
-rw-r--r--board/freescale/p2020come/MAINTAINERS7
-rw-r--r--board/freescale/p2020come/Makefile10
-rw-r--r--board/freescale/p2020come/ddr.c29
-rw-r--r--board/freescale/p2020come/law.c23
-rw-r--r--board/freescale/p2020come/p2020come.c275
-rw-r--r--board/freescale/p2020come/tlb.c83
-rw-r--r--board/freescale/p2020ds/Kconfig12
-rw-r--r--board/freescale/p2020ds/MAINTAINERS10
-rw-r--r--board/freescale/p2020ds/Makefile12
-rw-r--r--board/freescale/p2020ds/ddr.c129
-rw-r--r--board/freescale/p2020ds/law.c20
-rw-r--r--board/freescale/p2020ds/p2020ds.c263
-rw-r--r--board/freescale/p2020ds/tlb.c90
-rw-r--r--board/freescale/t102xqds/ddr.c19
-rw-r--r--board/freescale/t102xqds/t102xqds.c23
-rw-r--r--board/freescale/t102xrdb/cpld.h4
-rw-r--r--board/freescale/t102xrdb/ddr.c19
-rw-r--r--board/freescale/t102xrdb/eth_t102xrdb.c30
-rw-r--r--board/freescale/t102xrdb/spl.c7
-rw-r--r--board/freescale/t102xrdb/t102xrdb.c54
-rw-r--r--board/freescale/t1040qds/ddr.c19
-rw-r--r--board/freescale/t1040qds/eth.c93
-rw-r--r--board/freescale/t1040qds/t1040qds.c23
-rw-r--r--board/freescale/t104xrdb/MAINTAINERS1
-rw-r--r--board/freescale/t104xrdb/eth.c59
-rw-r--r--board/freescale/t4rdb/eth.c2
-rw-r--r--board/freescale/t4rdb/t4_rcw.cfg4
62 files changed, 525 insertions, 3413 deletions
diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS
index db2e5e3..3308839 100644
--- a/board/freescale/c29xpcie/MAINTAINERS
+++ b/board/freescale/c29xpcie/MAINTAINERS
@@ -6,3 +6,5 @@ F: include/configs/C29XPCIE.h
F: configs/C29XPCIE_defconfig
F: configs/C29XPCIE_NAND_defconfig
F: configs/C29XPCIE_SPIFLASH_defconfig
+F: configs/C29XPCIE_NOR_SECBOOT_defconfig
+F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 5f7a67d..1eb3786 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@ int pib_init(void)
#endif
#if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8360EMDS) || defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_MPC8569MDS)
val8 = 0;
i2c_write(0x20, 0x6, 1, &val8, 1);
i2c_write(0x20, 0x7, 1, &val8, 1);
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index c8ca674..745847c 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -27,3 +27,4 @@ F: configs/P5040DS_defconfig
F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
+F: configs/P5040DS_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS
index 638833d..661526b 100644
--- a/board/freescale/ls1021aqds/MAINTAINERS
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -6,6 +6,7 @@ F: include/configs/ls1021aqds.h
F: configs/ls1021aqds_nor_defconfig
F: configs/ls1021aqds_ddr4_nor_defconfig
F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F: configs/ls1021aqds_nor_lpuart_defconfig
F: configs/ls1021aqds_sdcard_defconfig
F: configs/ls1021aqds_qspi_defconfig
F: configs/ls1021aqds_nand_defconfig
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 3b6903c..ab02344 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,3 +7,4 @@
obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
new file mode 100644
index 0000000..90f5bc0
--- /dev/null
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd->bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 1000000000);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+ int ret;
+ u8 ch;
+
+ /* Mux I2C3+I2C4 as HSYNC+VSYNC */
+ ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to read I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+ ch &= 0x1F;
+ ch |= 0xA0;
+ ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+ 1, &ch, 1);
+ if (ret) {
+ printf("Error: failed to write I2C @%02x\n",
+ CONFIG_SYS_I2C_QIXIS_ADDR);
+ return ret;
+ }
+
+ if (strncmp(port, "hdmi", 4) == 0) {
+ unsigned long pixval;
+
+ name = "HDMI";
+
+ pixval = 1000000000 / dcu_fb_videomode->pixclock;
+ pixval *= 1000;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+ select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+ diu_set_dvi_encoder(pixval);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ } else {
+ return 0;
+ }
+
+ printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index a539ff9..6435bf9 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
}
#endif
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)
#else
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index f08e54f..20eade4 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -20,6 +20,7 @@
#include <fsl_sec.h>
#include <spl.h>
+#include "../common/sleep.h"
#include "../common/qixis.h"
#include "ls1021aqds_qixis.h"
#ifdef CONFIG_U_QE
@@ -48,6 +49,12 @@ enum {
MUX_TYPE_SD_PC_SG_SG,
};
+enum {
+ GE0_CLK125,
+ GE2_CLK125,
+ GE1_CLK125,
+};
+
int checkboard(void)
{
#ifndef CONFIG_QSPI_BOOT
@@ -177,7 +184,6 @@ int board_early_init_f(void)
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
- out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC
@@ -188,6 +194,24 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -195,6 +219,11 @@ int board_early_init_f(void)
* allow barrier transaction to DDR again */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
return 0;
}
@@ -219,9 +248,6 @@ void board_init_f(ulong dummy)
pinctl);
#endif
- /* Set global data pointer */
- gd = &gdata;
-
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -231,6 +257,11 @@ void board_init_f(ulong dummy)
get_clocks();
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
preloader_console_init();
#ifdef CONFIG_SPL_I2C_SUPPORT
@@ -244,6 +275,32 @@ void board_init_f(ulong dummy)
}
#endif
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ switch (etsec_gtx_125_mux) {
+ case GE0_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+ debug("etseccm set to GE0_CLK125\n");
+ break;
+
+ case GE2_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+ debug("etseccm set to GE2_CLK125\n");
+ break;
+
+ case GE1_CLK125:
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+ debug("etseccm set to GE1_CLK125\n");
+ break;
+
+ default:
+ printf("Error! trying to set etseccm to invalid value\n");
+ break;
+ }
+}
+
int config_board_mux(int ctrl_type)
{
u8 reg12, reg14;
@@ -253,6 +310,7 @@ int config_board_mux(int ctrl_type)
switch (ctrl_type) {
case MUX_TYPE_CAN:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
break;
case MUX_TYPE_IIC2:
@@ -262,6 +320,7 @@ int config_board_mux(int ctrl_type)
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
break;
case MUX_TYPE_SAI:
+ config_etseccm_source(GE2_CLK125);
reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
break;
case MUX_TYPE_SDHC:
@@ -474,13 +533,6 @@ int board_init(void)
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -503,6 +555,21 @@ int board_init(void)
return 0;
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+ struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+ enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
index 09b3be2..8e482eb 100644
--- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h
+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -32,4 +32,6 @@
#define QIXIS_SRDS1CLK_100 0x0
+#define QIXIS_DCU_BRDCFG5 0x55
+
#endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS
index 9176706..e9f6f0a 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -5,5 +5,6 @@ F: board/freescale/ls1021atwr/
F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F: configs/ls1021atwr_nor_lpuart_defconfig
F: configs/ls1021atwr_sdcard_defconfig
F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 8ab229d..bc8b006 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -263,6 +263,7 @@ int config_serdes_mux(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -281,15 +282,26 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
return 0;
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
- /* Set global data pointer */
- gd = &gdata;
-
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
@@ -408,16 +420,6 @@ struct smmu_stream_id dev_stream_id[] = {
int board_init(void)
{
- struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#ifndef CONFIG_QSPI_BOOT
diff --git a/board/freescale/mpc8360emds/Kconfig b/board/freescale/mpc8360emds/Kconfig
deleted file mode 100644
index 3f4f95c..0000000
--- a/board/freescale/mpc8360emds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360EMDS
-
-config SYS_BOARD
- default "mpc8360emds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360EMDS"
-
-endif
diff --git a/board/freescale/mpc8360emds/MAINTAINERS b/board/freescale/mpc8360emds/MAINTAINERS
deleted file mode 100644
index 91ff2ef..0000000
--- a/board/freescale/mpc8360emds/MAINTAINERS
+++ /dev/null
@@ -1,15 +0,0 @@
-MPC8360EMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
-F: board/freescale/mpc8360emds/
-F: include/configs/MPC8360EMDS.h
-F: configs/MPC8360EMDS_33_defconfig
-F: configs/MPC8360EMDS_33_ATM_defconfig
-F: configs/MPC8360EMDS_33_HOST_33_defconfig
-F: configs/MPC8360EMDS_33_HOST_66_defconfig
-F: configs/MPC8360EMDS_33_SLAVE_defconfig
-F: configs/MPC8360EMDS_66_defconfig
-F: configs/MPC8360EMDS_66_ATM_defconfig
-F: configs/MPC8360EMDS_66_HOST_33_defconfig
-F: configs/MPC8360EMDS_66_HOST_66_defconfig
-F: configs/MPC8360EMDS_66_SLAVE_defconfig
diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile
deleted file mode 100644
index e8332ce..0000000
--- a/board/freescale/mpc8360emds/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360emds.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc8360emds/README b/board/freescale/mpc8360emds/README
deleted file mode 100644
index 6afa753..0000000
--- a/board/freescale/mpc8360emds/README
+++ /dev/null
@@ -1,155 +0,0 @@
-Freescale MPC8360EMDS Board
------------------------------------------
-1. Board Switches and Jumpers
-1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
- For some reason, the HW designers describe the switch settings
- in terms of 0 and 1, and then map that to physical switches where
- the label "On" refers to logic 0 and "Off" is logic 1.
-
- Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
- bits may contribute to signals that are numbered based at 0,
- and some of those signals may be high-bit-number-0 too. Heed
- well the names and labels and do not get confused.
-
- "Off" == 1
- "On" == 0
-
- SW18 is switch 18 as silk-screened onto the board.
- SW4[8] is the bit labeled 8 on Switch 4.
- SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
- SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
- SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
- and bits labeled 8 is set as "Off".
-
-1.1 There are three type boards for MPC8360E silicon up to now, They are
-
- * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
- * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
- * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
-
-1.2 For all the MPC8360EMDS Board
-
- First, make sure the board default setting is consistent with the
- document shipped with your board. Then apply the following setting:
- SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
- SW4[1-8]= 0011_0000 (Flash boot on local bus)
- SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
- SW10[1-8]= 0000_1000 (core PLL setting)
- SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
- JP6 1-2
- on board Oscillator: 66M
-
-1.3 Since different board/chip rev. combinations have AC timing issues,
- u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
- by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
-
- When the rev2.x silicon mount on these boards, and if you are using
- u-boot version after this patch, to make the ethernet interfaces usable,
- and to enable RGMII-ID on your board, you have to setup the jumpers
- correctly.
-
- * MPC8360E-MDS-PB PROTO
- nothing to do
- * MPC8360E-MDS-PB PILOT
- JP9 and JP8 should be ON
- * MPC8360EA-MDS-PB PROTO
- JP2 and JP3 should be ON
-
-2. Memory Map
-
-2.1. The memory map should look pretty much like this:
-
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
- 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
- 0xc000_0000 0xdfff_ffff Empty 512M
- 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
- 0xe020_0000 0xe02f_ffff Empty 1M
- 0xe030_0000 0xe03f_ffff PCI IO 1M
- 0xe040_0000 0xefff_ffff Empty 252M
- 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
- 0xf400_0000 0xf7ff_ffff Empty 64M
- 0xf800_0000 0xf800_7fff BCSR on CS1 32K
- 0xf800_8000 0xf800_ffff PIB CS4 32K
- 0xf801_0000 0xf801_7fff PIB CS5 32K
- 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
-
-
-3. Definitions
-
-3.1 Explanation of NEW definitions in:
-
- include/configs/MPC8360EMDS.h
-
- CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
- CONFIG_MPC8360 MPC8360 specific
- CONFIG_MPC8360EMDS MPC8360EMDS board specific
-
-4. Compilation
-
- MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
-
- Assuming you're using BASH shell:
-
- export CROSS_COMPILE=your-cross-compile-prefix
- cd u-boot
- make distclean
- make MPC8360EMDS_XX_config
- make
-
- MPC8360EMDS support ATM, PCI in host and slave mode.
-
- To make u-boot support ATM :
- 1) Make MPC8360EMDS_XX_ATM_config
-
- To make u-boot support PCI host 66M :
- 1) DIP SW support PCI mode as described in Section 1.1.
- 2) Make MPC8360EMDS_XX_HOST_66_config
-
- To make u-boot support PCI host 33M :
- 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
- 2) Make MPC8360EMDS_XX_HOST_33_config
-
- To make u-boot support PCI slave 66M :
- 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
- 2) Make MPC8360EMDS_XX_SLAVE_config
-
- (where XX is:
- 33 - 33.33MHz oscillator
- 66 - 66MHz oscillator)
-
-5. Downloading and Flashing Images
-
-5.0 Download over serial line using Kermit:
-
- loadb
- [Drop to kermit:
- ^\c
- send <u-boot-bin-image>
- c
- ]
-
-
- Or via tftp:
-
- tftp 10000 u-boot.bin
-
-5.1 Reflash U-boot Image using U-boot
-
- tftp 20000 u-boot.bin
- protect off fef00000 fef3ffff
- erase fef00000 fef3ffff
-
- cp.b 20000 fef00000 xxxx
-
- or
-
- cp.b 20000 fef00000 3ffff
-
-
-You have to supply the correct byte count with 'xxxx' from the TFTP result log.
-Maybe 3ffff will work too, that corresponds to the erased sectors.
-
-
-6. Notes
- 1) The console baudrate for MPC8360EMDS is 115200bps.
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
deleted file mode 100644
index f0a55f8..0000000
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <phy.h>
-#include <fsl_mdio.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#include <spd_sdram.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-#include <hwconfig.h>
-#include <fdt_support.h>
-#if defined(CONFIG_PQ_MDS_PIB)
-#include "../common/pq-mds-pib.h"
-#endif
-#include "../../../drivers/qe/uec.h"
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* GETH1 */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {1, 6, 1, 0, 3}, /* TxD4 */
- {1, 7, 1, 0, 1}, /* TxD5 */
- {1, 9, 1, 0, 2}, /* TxD6 */
- {1, 10, 1, 0, 2}, /* TxD7 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 13, 2, 0, 1}, /* RxD4 */
- {1, 1, 2, 0, 2}, /* RxD5 */
- {1, 0, 2, 0, 2}, /* RxD6 */
- {1, 4, 2, 0, 2}, /* RxD7 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 16, 2, 0, 1}, /* RX_ER */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
- /* GETH2 */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {1, 2, 1, 0, 1}, /* TxD4 */
- {1, 3, 1, 0, 2}, /* TxD5 */
- {1, 5, 1, 0, 3}, /* TxD6 */
- {1, 8, 1, 0, 3}, /* TxD7 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 27, 2, 0, 1}, /* RxD4 */
- {1, 12, 2, 0, 2}, /* RxD5 */
- {1, 13, 2, 0, 3}, /* RxD6 */
- {1, 11, 2, 0, 2}, /* RxD7 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 30, 2, 0, 1}, /* RX_ER */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
-
- {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
-};
-
-/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
-static int board_handle_erratum2(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
- return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
- REVID_MINOR(immr->sysconf.spridr) == 1;
-}
-
-int board_early_init_f(void)
-{
- const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
-
- /* Enable flash write */
- bcsr[0xa] &= ~0x04;
-
- /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
- if (REVID_MAJOR(immr->sysconf.spridr) == 2)
- bcsr[0xe] = 0x30;
-
- /* Enable second UART */
- bcsr[0x9] &= ~0x01;
-
- if (board_handle_erratum2()) {
- void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
-
- /*
- * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
- * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
- */
- setbits_be32(immap, 0x0c003000);
-
- /*
- * IMMR + 0x14AC[20:27] = 10101010
- * (data delay for both UCC's)
- */
- clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
- }
- return 0;
-}
-
-int board_early_init_r(void)
-{
- gd_t *gd;
-#ifdef CONFIG_PQ_MDS_PIB
- pib_init();
-#endif
- /*
- * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
- * So re-setup PCI MEM space used BAT5 after relocated to DDR
- */
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
- write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
- write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
- }
-
- return 0;
-}
-
-#ifdef CONFIG_UEC_ETH
-static uec_info_t uec_info[] = {
-#ifdef CONFIG_UEC_ETH1
- STD_UEC_INFO(1),
-#endif
-#ifdef CONFIG_UEC_ETH2
- STD_UEC_INFO(2),
-#endif
-};
-
-int board_eth_init(bd_t *bd)
-{
- if (board_handle_erratum2()) {
- int i;
-
- for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
- uec_info[i].enet_interface_type =
- PHY_INTERFACE_MODE_RGMII_RXID;
- uec_info[i].speed = SPEED_1000;
- }
- }
- return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
-}
-#endif /* CONFIG_UEC_ETH */
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-int fixed_sdram(void);
-static int sdram_init(unsigned int base);
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 lbc_sdram_size;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- lbc_sdram_size = sdram_init(msize * 1024 * 1024);
- if (!msize)
- msize = lbc_sdram_size;
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE;
- u32 ddr_size = msize << 20;
- u32 ddr_size_log2 = __ilog2(ddr_size);
- u32 half_ddr_size = ddr_size >> 1;
-
- im->sysconf.ddrlaw[0].bar =
- CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CONFIG_SYS_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-#ifdef CONFIG_DDR_II
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
-#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
-#warning Chip select bounds is only configurable in 16MB increments
-#endif
- im->ddr.csbnds[0].csbnds =
- ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
- im->ddr.csbnds[1].csbnds =
- (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
- CSBNDS_SA_SHIFT) & CSBNDS_SA) |
- (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
- CSBNDS_EA_SHIFT) & CSBNDS_EA);
-
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
-
- im->ddr.cs_config[2] = 0;
- im->ddr.cs_config[3] = 0;
-
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-#endif /*!CONFIG_SYS_SPD_EEPROM */
-
-int checkboard(void)
-{
- puts("Board: Freescale MPC8360EMDS\n");
- return 0;
-}
-
-/*
- * if MPC8360EMDS is soldered with SDRAM
- */
-#ifdef CONFIG_SYS_LB_SDRAM
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-static int sdram_init(unsigned int base)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbc = LBC_BASE_ADDR;
- const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
- int rem = base % sdram_size;
- uint *sdram_addr;
-
- /* window base address should be aligned to the window size */
- if (rem)
- base = base - rem + sdram_size;
-
- /*
- * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
- * After relocated to DDR, reuse BAT5 for PCI MEM space
- */
- if (base > CONFIG_MAX_MEM_MAPPED) {
- unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
- unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
-
- /* Setup the BAT6 for SDRAM */
- write_bat(DBAT6, batu, batl);
- write_bat(IBAT6, batu, batl);
- }
-
- sdram_addr = (uint *)base;
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_br(2, base | CONFIG_SYS_BR2);
- set_lbc_or(2, CONFIG_SYS_OR2);
- immap->sysconf.lblaw[2].bar = base;
- immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
-
- /*setup mtrpt, lsrt and lbcr for LB bus */
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * We need do 8 times auto refresh operation.
- */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- *sdram_addr = 0xff; /* 1 times */
- udelay(100);
- *sdram_addr = 0xff; /* 2 times */
- udelay(100);
- *sdram_addr = 0xff; /* 3 times */
- udelay(100);
- *sdram_addr = 0xff; /* 4 times */
- udelay(100);
- *sdram_addr = 0xff; /* 5 times */
- udelay(100);
- *sdram_addr = 0xff; /* 6 times */
- udelay(100);
- *sdram_addr = 0xff; /* 7 times */
- udelay(100);
- *sdram_addr = 0xff; /* 8 times */
- udelay(100);
-
- /* Mode register write operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- *(sdram_addr + 0xcc) = 0xff;
- udelay(100);
-
- /* Normal operation */
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- /*
- * In non-aligned case we don't [normally] use that memory because
- * there is a hole.
- */
- if (rem)
- return 0;
- return CONFIG_SYS_LBC_SDRAM_SIZE;
-}
-#else
-static int sdram_init(unsigned int base) { return 0; }
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
-{
- if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
- return;
-
- do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
- "peripheral", sizeof("peripheral"), 1);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
- ft_board_fixup_qe_usb(blob, bd);
- /*
- * mpc8360ea pb mds errata 2: RGMII timing
- * if on mpc8360ea rev. 2.1,
- * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
- */
- if (board_handle_erratum2()) {
- int nodeoffset;
- const char *prop;
- int path;
-
- nodeoffset = fdt_path_offset(blob, "/aliases");
- if (nodeoffset >= 0) {
-#if defined(CONFIG_HAS_ETH0)
- /* fixup UCC 1 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
-#if defined(CONFIG_HAS_ETH1)
- /* fixup UCC 2 if using rgmii-id mode */
- prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
- if (prop) {
- path = fdt_path_offset(blob, prop);
- prop = fdt_getprop(blob, path,
- "phy-connection-type", 0);
- if (prop && (strcmp(prop, "rgmii-id") == 0))
- fdt_fixup_phy_connection(blob, path,
- PHY_INTERFACE_MODE_RGMII_RXID);
- }
-#endif
- }
- }
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
deleted file mode 100644
index 71244df..0000000
--- a/board/freescale/mpc8360emds/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * PCI Configuration space access support for MPC83xx PCI Bridge
- */
-
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <i2c.h>
-#include <asm/fsl_i2c.h>
-#include "../common/pq-mds-pib.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct pci_region pci1_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-
-#ifdef CONFIG_MPC83XX_PCI2
-static struct pci_region pci2_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI2_MEM_BASE,
- phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
- size: CONFIG_SYS_PCI2_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI2_IO_BASE,
- phys_start: CONFIG_SYS_PCI2_IO_PHYS,
- size: CONFIG_SYS_PCI2_IO_SIZE,
- flags: PCI_REGION_IO
- },
- {
- bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
- size: CONFIG_SYS_PCI2_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
-};
-#endif
-
-void pci_init_board(void)
-#ifdef CONFIG_PCISLAVE
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
- struct pci_region *reg[] = { pci1_regions };
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- mpc83xx_pci_init(1, reg);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar0 = 0x0;
- pci_ctrl[0].pibar0 = 0x0;
- pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
- PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
-
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 &= ~PIWAR_EN;
-
- pci_ctrl[0].pitar2 = 0x0;
- pci_ctrl[0].pibar2 = 0x0;
- pci_ctrl[0].piebar2 = 0x0;
- pci_ctrl[0].piwar2 &= ~PIWAR_EN;
-
- /* Unlock the configuration bit */
- mpc83xx_pcislave_unlock(0);
- printf("PCI: Agent mode enabled\n");
-}
-#else
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
- struct pci_region *reg[] = { pci1_regions };
-#else
- struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
- /* initialize the PCA9555PW IO expander on the PIB board */
- pib_init();
-
-#if defined(CONFIG_PCI_66M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#elif defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
-
- udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
- mpc83xx_pci_init(1, reg);
-#else
- mpc83xx_pci_init(2, reg);
-#endif
-}
-#endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc8360erdk/Kconfig b/board/freescale/mpc8360erdk/Kconfig
deleted file mode 100644
index 5c9be7c..0000000
--- a/board/freescale/mpc8360erdk/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8360ERDK
-
-config SYS_BOARD
- default "mpc8360erdk"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8360ERDK"
-
-endif
diff --git a/board/freescale/mpc8360erdk/MAINTAINERS b/board/freescale/mpc8360erdk/MAINTAINERS
deleted file mode 100644
index e5b5995..0000000
--- a/board/freescale/mpc8360erdk/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC8360ERDK BOARD
-#M: Anton Vorontsov <avorontsov@ru.mvista.com>
-S: Orphan (since 2014-03)
-F: board/freescale/mpc8360erdk/
-F: include/configs/MPC8360ERDK.h
-F: configs/MPC8360ERDK_defconfig
-F: configs/MPC8360ERDK_33_defconfig
diff --git a/board/freescale/mpc8360erdk/Makefile b/board/freescale/mpc8360erdk/Makefile
deleted file mode 100644
index e2235c2..0000000
--- a/board/freescale/mpc8360erdk/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8360erdk.o
-obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
deleted file mode 100644
index 478f820..0000000
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * Copyright (C) 2007 Logic Product Development, Inc.
- * Peter Barada <peterb@logicpd.com>
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <libfdt.h>
-
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* MDIO */
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- /* UCC1 - UEC (Gigabit) */
- {0, 3, 1, 0, 1}, /* TxD0 */
- {0, 4, 1, 0, 1}, /* TxD1 */
- {0, 5, 1, 0, 1}, /* TxD2 */
- {0, 6, 1, 0, 1}, /* TxD3 */
- {0, 9, 2, 0, 1}, /* RxD0 */
- {0, 10, 2, 0, 1}, /* RxD1 */
- {0, 11, 2, 0, 1}, /* RxD2 */
- {0, 12, 2, 0, 1}, /* RxD3 */
- {0, 7, 1, 0, 1}, /* TX_EN */
- {0, 8, 1, 0, 1}, /* TX_ER */
- {0, 15, 2, 0, 1}, /* RX_DV */
- {0, 0, 2, 0, 1}, /* RX_CLK */
- {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
- {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
-
- /* UCC2 - UEC (Gigabit) */
- {0, 17, 1, 0, 1}, /* TxD0 */
- {0, 18, 1, 0, 1}, /* TxD1 */
- {0, 19, 1, 0, 1}, /* TxD2 */
- {0, 20, 1, 0, 1}, /* TxD3 */
- {0, 23, 2, 0, 1}, /* RxD0 */
- {0, 24, 2, 0, 1}, /* RxD1 */
- {0, 25, 2, 0, 1}, /* RxD2 */
- {0, 26, 2, 0, 1}, /* RxD3 */
- {0, 21, 1, 0, 1}, /* TX_EN */
- {0, 22, 1, 0, 1}, /* TX_ER */
- {0, 29, 2, 0, 1}, /* RX_DV */
- {0, 31, 2, 0, 1}, /* RX_CLK */
- {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */
- {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
-
- /* UCC7 - UEC */
- {4, 0, 1, 0, 1}, /* TxD0 */
- {4, 1, 1, 0, 1}, /* TxD1 */
- {4, 2, 1, 0, 1}, /* TxD2 */
- {4, 3, 1, 0, 1}, /* TxD3 */
- {4, 6, 2, 0, 1}, /* RxD0 */
- {4, 7, 2, 0, 1}, /* RxD1 */
- {4, 8, 2, 0, 1}, /* RxD2 */
- {4, 9, 2, 0, 1}, /* RxD3 */
- {4, 4, 1, 0, 1}, /* TX_EN */
- {4, 5, 1, 0, 1}, /* TX_ER */
- {4, 12, 2, 0, 1}, /* RX_DV */
- {4, 13, 2, 0, 1}, /* RX_ER */
- {4, 10, 2, 0, 1}, /* COL */
- {4, 11, 2, 0, 1}, /* CRS */
- {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */
- {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */
-
- /* UCC4 - UEC */
- {1, 14, 1, 0, 1}, /* TxD0 */
- {1, 15, 1, 0, 1}, /* TxD1 */
- {1, 16, 1, 0, 1}, /* TxD2 */
- {1, 17, 1, 0, 1}, /* TxD3 */
- {1, 20, 2, 0, 1}, /* RxD0 */
- {1, 21, 2, 0, 1}, /* RxD1 */
- {1, 22, 2, 0, 1}, /* RxD2 */
- {1, 23, 2, 0, 1}, /* RxD3 */
- {1, 18, 1, 0, 1}, /* TX_EN */
- {1, 19, 1, 0, 2}, /* TX_ER */
- {1, 26, 2, 0, 1}, /* RX_DV */
- {1, 27, 2, 0, 1}, /* RX_ER */
- {1, 24, 2, 0, 1}, /* COL */
- {1, 25, 2, 0, 1}, /* CRS */
- {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */
- {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */
-
- /* PCI1 */
- {5, 4, 2, 0, 3}, /* PCI_M66EN */
- {5, 5, 1, 0, 3}, /* PCI_INTA */
- {5, 6, 1, 0, 3}, /* PCI_RSTO */
- {5, 7, 3, 0, 3}, /* PCI_C_BE0 */
- {5, 8, 3, 0, 3}, /* PCI_C_BE1 */
- {5, 9, 3, 0, 3}, /* PCI_C_BE2 */
- {5, 10, 3, 0, 3}, /* PCI_C_BE3 */
- {5, 11, 3, 0, 3}, /* PCI_PAR */
- {5, 12, 3, 0, 3}, /* PCI_FRAME */
- {5, 13, 3, 0, 3}, /* PCI_TRDY */
- {5, 14, 3, 0, 3}, /* PCI_IRDY */
- {5, 15, 3, 0, 3}, /* PCI_STOP */
- {5, 16, 3, 0, 3}, /* PCI_DEVSEL */
- {5, 17, 0, 0, 0}, /* PCI_IDSEL */
- {5, 18, 3, 0, 3}, /* PCI_SERR */
- {5, 19, 3, 0, 3}, /* PCI_PERR */
- {5, 20, 3, 0, 3}, /* PCI_REQ0 */
- {5, 21, 2, 0, 3}, /* PCI_REQ1 */
- {5, 22, 2, 0, 3}, /* PCI_GNT2 */
- {5, 23, 3, 0, 3}, /* PCI_GNT0 */
- {5, 24, 1, 0, 3}, /* PCI_GNT1 */
- {5, 25, 1, 0, 3}, /* PCI_GNT2 */
- {5, 26, 0, 0, 0}, /* PCI_CLK0 */
- {5, 27, 0, 0, 0}, /* PCI_CLK1 */
- {5, 28, 0, 0, 0}, /* PCI_CLK2 */
- {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */
- {6, 0, 3, 0, 3}, /* PCI_AD0 */
- {6, 1, 3, 0, 3}, /* PCI_AD1 */
- {6, 2, 3, 0, 3}, /* PCI_AD2 */
- {6, 3, 3, 0, 3}, /* PCI_AD3 */
- {6, 4, 3, 0, 3}, /* PCI_AD4 */
- {6, 5, 3, 0, 3}, /* PCI_AD5 */
- {6, 6, 3, 0, 3}, /* PCI_AD6 */
- {6, 7, 3, 0, 3}, /* PCI_AD7 */
- {6, 8, 3, 0, 3}, /* PCI_AD8 */
- {6, 9, 3, 0, 3}, /* PCI_AD9 */
- {6, 10, 3, 0, 3}, /* PCI_AD10 */
- {6, 11, 3, 0, 3}, /* PCI_AD11 */
- {6, 12, 3, 0, 3}, /* PCI_AD12 */
- {6, 13, 3, 0, 3}, /* PCI_AD13 */
- {6, 14, 3, 0, 3}, /* PCI_AD14 */
- {6, 15, 3, 0, 3}, /* PCI_AD15 */
- {6, 16, 3, 0, 3}, /* PCI_AD16 */
- {6, 17, 3, 0, 3}, /* PCI_AD17 */
- {6, 18, 3, 0, 3}, /* PCI_AD18 */
- {6, 19, 3, 0, 3}, /* PCI_AD19 */
- {6, 20, 3, 0, 3}, /* PCI_AD20 */
- {6, 21, 3, 0, 3}, /* PCI_AD21 */
- {6, 22, 3, 0, 3}, /* PCI_AD22 */
- {6, 23, 3, 0, 3}, /* PCI_AD23 */
- {6, 24, 3, 0, 3}, /* PCI_AD24 */
- {6, 25, 3, 0, 3}, /* PCI_AD25 */
- {6, 26, 3, 0, 3}, /* PCI_AD26 */
- {6, 27, 3, 0, 3}, /* PCI_AD27 */
- {6, 28, 3, 0, 3}, /* PCI_AD28 */
- {6, 29, 3, 0, 3}, /* PCI_AD29 */
- {6, 30, 3, 0, 3}, /* PCI_AD30 */
- {6, 31, 3, 0, 3}, /* PCI_AD31 */
-
- /* NAND */
- {4, 18, 2, 0, 0}, /* NAND_RYnBY */
-
- /* DUART - UART2 */
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
-
- /* UCC5 - UART3 */
- {3, 0, 1, 0, 1}, /* UART3_TX */
- {3, 4, 1, 0, 1}, /* UART3_RTS */
- {3, 6, 2, 0, 1}, /* UART3_RX */
- {3, 12, 2, 0, 0}, /* UART3_CTS */
- {3, 13, 2, 0, 0}, /* UCC5_CD */
-
- /* UCC6 - UART4 */
- {3, 14, 1, 0, 1}, /* UART4_TX */
- {3, 18, 1, 0, 1}, /* UART4_RTS */
- {3, 20, 2, 0, 1}, /* UART4_RX */
- {3, 26, 2, 0, 0}, /* UART4_CTS */
- {3, 27, 2, 0, 0}, /* UCC6_CD */
-
- /* Fujitsu MB86277 (MINT) graphics controller */
- {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */
- {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */
- {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */
- {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */
-
- /* AD7843 ADC/Touchscreen controller */
- {4, 14, 1, 0, 0}, /* SPI_nCS0 */
- {4, 28, 3, 0, 3}, /* SPI_MOSI */
- {4, 29, 3, 0, 3}, /* SPI_MISO */
- {4, 30, 3, 0, 3}, /* SPI_CLK */
-
- /* Freescale QUICC Engine USB Host Controller (FHCI) */
- {1, 2, 1, 0, 3}, /* USBOE */
- {1, 3, 1, 0, 3}, /* USBTP */
- {1, 8, 1, 0, 1}, /* USBTN */
- {1, 9, 2, 1, 3}, /* USBRP */
- {1, 10, 2, 0, 3}, /* USBRXD */
- {1, 11, 2, 1, 3}, /* USBRN */
- {2, 20, 2, 0, 1}, /* CLK21 */
- {4, 20, 1, 0, 0}, /* SPEED */
- {4, 21, 1, 0, 0}, /* SUSPND */
-
- /* END of table */
- {0, 0, 0, 0, QE_IOP_TAB_END},
-};
-
-int board_early_init_r(void)
-{
- void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
- u32 val;
-
- /*
- * Because of errata in the UCCs, we have to write to the reserved
- * registers to slow the clocks down.
- */
- val = in_be32(reg);
- /* UCC1 */
- val |= 0x00003000;
- /* UCC2 */
- val |= 0x0c000000;
- out_be32(reg, val);
-
- return 0;
-}
-
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
-
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
- im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
- im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
- im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
- im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
- im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
- im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
- im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
- udelay(200);
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-
-phys_size_t initdram(int board_type)
-{
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
- msize = fixed_sdram();
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize DDR ECC byte
- */
- ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-int checkboard(void)
-{
- puts("Board: Freescale/Logic MPC8360ERDK\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
- .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
- .size = CONFIG_SYS_PCI1_MEM_SIZE,
- .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
- .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
- .size = CONFIG_SYS_PCI1_MMIO_SIZE,
- .flags = PCI_REGION_MEM,
- },
- {
- .bus_start = CONFIG_SYS_PCI1_IO_BASE,
- .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
- .size = CONFIG_SYS_PCI1_IO_SIZE,
- .flags = PCI_REGION_IO,
- },
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions, };
-
-#if defined(CONFIG_PCI_33M)
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
- OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
- printf("PCI clock is 33MHz\n");
-#else
- clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
- printf("PCI clock is 66MHz\n");
-#endif
-
- udelay(2000);
-
- /* Configure PCI Local Access Windows */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
- ft_pci_setup(blob, bd);
-
- return 0;
-}
-#endif
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
deleted file mode 100644
index 237c0c4..0000000
--- a/board/freescale/mpc8360erdk/nand.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * MPC8360E-RDK support for the NAND on FSL UPM
- *
- * Copyright (C) 2007 MontaVista Software, Inc.
- * Anton Vorontsov <avorontsov@ru.mvista.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/immap_83xx.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/fsl_upm.h>
-#include <nand.h>
-
-static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
-
-static const u32 upm_array[] = {
- 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
- 0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
- 0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
- 0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
- 0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
- 0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
- 0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
- 0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
- 0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
- 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
- 0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
- 0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
-};
-
-static void upm_setup(struct fsl_upm *upm)
-{
- int i;
-
- /* write upm array */
- out_be32(upm->mxmr, MxMR_OP_WARR);
-
- for (i = 0; i < 64; i++) {
- out_be32(upm->mdr, upm_array[i]);
- out_8(upm->io_addr, 0x0);
- }
-
- /* normal operation */
- out_be32(upm->mxmr, MxMR_OP_NORM);
- while (in_be32(upm->mxmr) != MxMR_OP_NORM)
- eieio();
-}
-
-static int dev_ready(int chip_nr)
-{
- if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
- debug("nand ready\n");
- return 1;
- }
-
- debug("nand busy\n");
- return 0;
-}
-
-static struct fsl_upm_nand fun = {
- .upm = {
- .io_addr = (void *)CONFIG_SYS_NAND_BASE,
- },
- .width = 8,
- .upm_cmd_offset = 8,
- .upm_addr_offset = 16,
- .dev_ready = dev_ready,
- .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
- .chip_delay = 50,
-};
-
-int board_nand_init(struct nand_chip *nand)
-{
- fun.upm.mxmr = &im->im_lbc.mamr;
- fun.upm.mdr = &im->im_lbc.mdr;
- fun.upm.mar = &im->im_lbc.mar;
-
- upm_setup(&fun.upm);
-
- return fsl_upm_nand_init(nand, &fun);
-}
diff --git a/board/freescale/mpc837xerdb/MAINTAINERS b/board/freescale/mpc837xerdb/MAINTAINERS
index 8592a2c..81b4eed 100644
--- a/board/freescale/mpc837xerdb/MAINTAINERS
+++ b/board/freescale/mpc837xerdb/MAINTAINERS
@@ -1,6 +1,6 @@
MPC837XERDB BOARD
-#M: Joe D'Abbraccio <ljd015@freescale.com>
-S: Orphan (since 2014-06)
+M: Sinan Akman <sinan@writeme.com>
+S: Maintained
F: board/freescale/mpc837xerdb/
F: include/configs/MPC837XERDB.h
F: configs/MPC837XERDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Kconfig b/board/freescale/p1_p2_rdb/Kconfig
deleted file mode 100644
index d7ad35d..0000000
--- a/board/freescale/p1_p2_rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P1_P2_RDB
-
-config SYS_BOARD
- default "p1_p2_rdb"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P1_P2_RDB"
-
-endif
diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS
deleted file mode 100644
index aabf587..0000000
--- a/board/freescale/p1_p2_rdb/MAINTAINERS
+++ /dev/null
@@ -1,37 +0,0 @@
-P1_P2_RDB BOARD
-#M: -
-S: Maintained
-F: board/freescale/p1_p2_rdb/
-F: include/configs/P1_P2_RDB.h
-F: configs/P1011RDB_defconfig
-F: configs/P1011RDB_36BIT_defconfig
-F: configs/P1011RDB_36BIT_SDCARD_defconfig
-F: configs/P1011RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1011RDB_NAND_defconfig
-F: configs/P1011RDB_SDCARD_defconfig
-F: configs/P1011RDB_SPIFLASH_defconfig
-F: configs/P1020RDB_defconfig
-F: configs/P1020RDB_36BIT_defconfig
-F: configs/P1020RDB_36BIT_SDCARD_defconfig
-F: configs/P1020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P1020RDB_NAND_defconfig
-F: configs/P1020RDB_SDCARD_defconfig
-F: configs/P1020RDB_SPIFLASH_defconfig
-F: configs/P2010RDB_defconfig
-F: configs/P2010RDB_36BIT_defconfig
-F: configs/P2010RDB_36BIT_SDCARD_defconfig
-F: configs/P2010RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2010RDB_NAND_defconfig
-F: configs/P2010RDB_SDCARD_defconfig
-F: configs/P2010RDB_SPIFLASH_defconfig
-F: configs/P2020RDB_36BIT_defconfig
-F: configs/P2020RDB_36BIT_SDCARD_defconfig
-F: configs/P2020RDB_36BIT_SPIFLASH_defconfig
-F: configs/P2020RDB_NAND_defconfig
-F: configs/P2020RDB_SDCARD_defconfig
-F: configs/P2020RDB_SPIFLASH_defconfig
-
-P2020RDB BOARD
-M: Poonam Aggrwal <poonam.aggrwal@freescale.com>
-S: Maintained
-F: configs/P2020RDB_defconfig
diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
deleted file mode 100644
index a97bf45..0000000
--- a/board/freescale/p1_p2_rdb/Makefile
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-
-obj-y += spl_minimal.o tlb.o law.o
-
-else
-ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
-else
-obj-y += p1_p2_rdb.o
-obj-$(CONFIG_PCI) += pci.o
-endif
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
-
-endif
diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README
deleted file mode 100644
index cd66e58..0000000
--- a/board/freescale/p1_p2_rdb/README
+++ /dev/null
@@ -1,145 +0,0 @@
-Overview
---------
-P2020RDB is a Low End Dual core platform supporting the P2020 processor
-of QorIQ series. P2020 is an e500 based dual core SOC.
-
-Building U-boot
------------
-To build the u-boot for P2020RDB:
- make P2020RDB_config
- make
-
-NOR Flash Banks
------------
-RDB board for P2020 has two flash banks. They are both present on boot.
-
-Booting by default is always from the boot bank at 0xef00_0000.
-
-Memory Map
-----------
-0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
-0xe800_0000 - 0xefff_ffff Boot bank 8MB
-
-0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB
-0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB
-
-Switch settings to boot from the NOR flash banks
-------------------------------------------------
-SW4[8]=0 default NOR Flash bank
-SW4[8]=1 Alternate NOR Flash bank
-
-Flashing Images
----------------
-To place a new u-boot image in the alternate flash bank and then boot
-with that new image temporarily, use this:
- tftp 1000000 u-boot.bin
- erase ef740000 ef7fffff
- cp.b 1000000 ef740000 c0000
-
-Now to boot from the alternate bank change the SW4[8] from 0 to 1.
-
-To program the image in the boot flash bank:
- tftp 1000000 u-boot.bin
- protect off all
- erase eff40000 ffffffff
- cp.b 1000000 eff40000 c0000
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
- dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
-
-Likely, that .dts file will come from here;
-
- linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
- tftp 1000000 uImage.p2020rdb
- tftp 2000000 rootfs.ext2.gz.uboot
- tftp c00000 p2020rdb.dtb
- bootm 1000000 2000000 c00000
-
-Implementing AMP(Asymmetric MultiProcessing)
----------------------------------------------
-1. Build kernel image for core0:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - un-select "Processor support"->
- "Symetric multi-processing support"
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
-
-2. Build kernel image for core1:
-
- a. $ make 85xx/p1_p2_rdb_defconfig
-
- b. $ make menuconfig
- - Un-select "Processor support"->
- "Symetric multi-processing support"
- - Select "Advanced setup" ->
- "Prompt for advanced kernel configuration options"
- - Select
- "Set physical address where the kernel is loaded"
- and set it to 0x20000000, assuming core1 will
- start from 512MB.
- - Select "Set custom page offset address"
- - Select "Set custom kernel base address"
- - Select "Set maximum low memory"
- - "Exit" and save the selection.
-
- c. $ make uImage
-
- d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
-
-3. Create dtb for core0:
-
- $ dtc -I dts -O dtb -f -b 0
- arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
- /tftpboot/p2020rdb_camp_core0.dtb
-
-4. Create dtb for core1:
-
- $ dtc -I dts -O dtb -f -b 1
- arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
- /tftpboot/p2020rdb_camp_core1.dtb
-
-5. Bring up two cores separately:
-
- a. Power on the board, under u-boot prompt:
- => setenv <serverip>
- => setenv <ipaddr>
- => setenv bootargs root=/dev/ram rw console=ttyS0,115200
- b. Bring up core1's kernel first:
- => setenv bootm_low 0x20000000
- => setenv bootm_size 0x10000000
- => tftp 21000000 uImage.core1
- => tftp 22000000 ramdiskfile
- => tftp 20c00000 p2020rdb_camp_core1.dtb
- => interrupts off
- => bootm start 21000000 22000000 20c00000
- => bootm loados
- => bootm ramdisk
- => bootm fdt
- => fdt boardsetup
- => fdt chosen $initrd_start $initrd_end
- => bootm prep
- => cpu 1 release $bootm_low - $fdtaddr -
- c. Bring up core0's kernel(on the same u-boot console):
- => setenv bootm_low 0
- => setenv bootm_size 0x20000000
- => tftp 1000000 uImage.core0
- => tftp 2000000 ramdiskfile
- => tftp c00000 p2020rdb_camp_core0.dtb
- => bootm 1000000 2000000 c00000
-
-Please note only core0 will run u-boot, core1 starts kernel directly
-after "cpu release" command is issued.
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
deleted file mode 100644
index 98ee5f1..0000000
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00000000
-#define CONFIG_SYS_DDR_TIMING_5 0x00000000
-
-#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
-#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
-#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
-#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
-#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
-
-#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
-#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
-#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
-#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
-
-#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
-#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
-#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
-#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
-#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
-
-#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
-#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
-#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
-#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
-#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
- .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
- .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
- .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
- .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
- .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
- .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
- .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
- .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
- .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
- .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
- .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
- .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
- .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
- .ddr_data_init = CONFIG_MEM_INIT_VALUE,
- .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
- .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
- .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
- .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
- .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
- .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
- .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
- .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
- .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
- .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram (void)
-{
- fsl_ddr_cfg_regs_t ddr_cfg_regs;
- size_t ddr_size;
- struct cpu_type *cpu;
- ulong ddr_freq, ddr_freq_mhz;
-
- cpu = gd->arch.cpu;
-
- ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return ddr_size;
-#endif
- ddr_freq = get_ddr_freq(0);
- ddr_freq_mhz = ddr_freq / 1000000;
-
- printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
-
- if(ddr_freq_mhz <= 400)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 533)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 667)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
- else if(ddr_freq_mhz <= 800)
- memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
- else
- panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
-
- /* P1020 and it's derivatives support max 32bit DDR width */
- if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
- ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
- ddr_cfg_regs.cs[0].bnds = 0x0000001F;
- }
-
- fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
- set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
- return ddr_size;
-}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
deleted file mode 100644
index b60a27f..0000000
--- a/board/freescale/p1_p2_rdb/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
deleted file mode 100644
index 61ed466..0000000
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <rtc.h>
-#include <i2c.h>
-#include <hwconfig.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define VSC7385_RST_SET 0x00080000
-#define SLIC_RST_SET 0x00040000
-#define SGMII_PHY_RST_SET 0x00020000
-#define PCIE_RST_SET 0x00010000
-#define RGMII_PHY_RST_SET 0x02000000
-
-#define USB_RST_CLR 0x04000000
-#define USB2_PORT_OUT_EN 0x01000000
-
-#define GPIO_DIR 0x060f0000
-
-#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if(sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
- return 0;
-}
-#endif
-
-int checkboard (void)
-{
- u32 val_gpdat, board_rev_gpio;
- volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- char board_rev = 0;
- struct cpu_type *cpu;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- board_rev_gpio = val_gpdat & BOARDREV_MASK;
- if (board_rev_gpio == BOARDREV_C)
- board_rev = 'C';
- else if (board_rev_gpio == BOARDREV_D)
- board_rev = 'D';
- else
- panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
-
- cpu = gd->arch.cpu;
- printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-
- setbits_be32(&pgpio->gpdir, GPIO_DIR);
-
-/*
- * Bringing the following peripherals out of reset via GPIOs
- * 0 = reset and 1 = out of reset
- * GPIO12 - Reset to Ethernet Switch
- * GPIO13 - Reset to SLIC/SLAC devices
- * GPIO14 - Reset to SGMII_PHY_N
- * GPIO15 - Reset to PCIe slots
- * GPIO6 - Reset to RGMII PHY
- * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
- */
- clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
-
- setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
- setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
-#endif
- return 0;
-}
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- unsigned int orig_bus = i2c_get_bus_num();
- u8 i2c_data;
-
- i2c_set_bus_num(1);
- if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
- 1, &i2c_data, sizeof(i2c_data)) == 0) {
- if (i2c_data & 0x2)
- puts("NOR Flash Bank : Secondary\n");
- else
- puts("NOR Flash Bank : Primary\n");
-
- if (i2c_data & 0x1) {
- setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
- puts("SD/MMC : 8-bit Mode\n");
- puts("eSPI : Disabled\n");
- } else {
- puts("SD/MMC : 4-bit Mode\n");
- puts("eSPI : Enabled\n");
- }
- } else {
- puts("Failed reading I2C Chip 0x18 on bus 1\n");
- }
- i2c_set_bus_num(orig_bus);
-
- /*
- * Remap Boot flash region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_16M, 1);
- rtc_reset();
- return 0;
-}
-
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
- char *tmp;
- unsigned int vscfw_addr;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-#ifdef CONFIG_VSC7385_ENET
-/* If a VSC7385 microcode image is present, then upload it. */
- if ((tmp = getenv ("vscfw_addr")) != NULL) {
- vscfw_addr = simple_strtoul (tmp, NULL, 16);
- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
- if (vsc7385_upload_firmware((void *) vscfw_addr,
- CONFIG_VSC7385_IMAGE_SIZE))
- puts("Failure uploading VSC7385 microcode.\n");
- } else
- puts("No address specified for VSC7385 microcode.\n");
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_pci_board_setup(void *blob);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif /* #if defined(CONFIG_PCI) */
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
-#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
- /* Delete eLBC node as it is muxed with USB2 controller */
- if (hwconfig("usb2")) {
- const char *soc_elbc_compat = "fsl,p1020-elbc";
- int off = fdt_node_offset_by_compatible(blob, -1,
- soc_elbc_compat);
- if (off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_elbc_compat);
- return off;
- }
- err = fdt_del_node(blob, off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n",
- soc_elbc_compat);
- return err;
- }
- return 0;
- }
-#endif
- /* Delete USB2 node as it is muxed with eLBC */
- usb1_off = fdt_node_offset_by_compatible(blob, -1,
- soc_usb_compat);
- if (usb1_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb1_off;
- }
- usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
- soc_usb_compat);
- if (usb2_off < 0) {
- printf("WARNING: could not find compatible node %s\n",
- soc_usb_compat);
- return usb2_off;
- }
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
- printf("WARNING: could not remove %s\n", soc_usb_compat);
- return err;
- }
-
- return 0;
-}
-
-#endif
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
deleted file mode 100644
index 745ebb1..0000000
--- a/board/freescale/p1_p2_rdb/pci.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c
deleted file mode 100644
index f30c5fe..0000000
--- a/board/freescale/p1_p2_rdb/spl.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <nand.h>
-#include <i2c.h>
-#include <fsl_esdhc.h>
-#include <spi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-phys_size_t get_effective_memsize(void)
-{
- return CONFIG_SYS_L2_SIZE;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio, bus_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- console_init_f();
-
- /* Set pmuxcr to allow both i2c1 and i2c2 */
- setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
- setbits_be32(&gur->pmuxcr,
- in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
-
- /* Read back the register to synchronize the write. */
- in_be32(&gur->pmuxcr);
-
-#ifdef CONFIG_SPL_SPI_BOOT
- clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- gd->bus_clk = bus_clk;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-#ifdef CONFIG_SPL_MMC_BOOT
- puts("\nSD boot...\n");
-#elif defined(CONFIG_SPL_SPI_BOOT)
- puts("\nSPI Flash boot...\n");
-#endif
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
-
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
-
- probecpu();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
- CONFIG_SPL_RELOC_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_initialize(bd);
-#endif
- /* relocate environment function pointers etc. */
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_NAND_BOOT
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-#ifdef CONFIG_SPL_SPI_BOOT
- spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_ENV_ADDR);
-#endif
-
- gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
- gd->env_valid = 1;
-
- gd->ram_size = initdram(0);
-#ifdef CONFIG_SPL_NAND_BOOT
- puts("Tertiary program loader running in sram...");
-#else
- puts("Second program loader running in sram...\n");
-#endif
-
-#ifdef CONFIG_SPL_MMC_BOOT
- mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
- spi_boot();
-#elif defined(CONFIG_SPL_NAND_BOOT)
- nand_boot();
-#endif
-}
diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c
deleted file mode 100644
index 96a4d1c..0000000
--- a/board/freescale/p1_p2_rdb/spl_minimal.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 val_gpdat, sysclk_gpio;
-
- val_gpdat = in_be32(&pgpio->gpdat);
- sysclk_gpio = val_gpdat & SYSCLK_MASK;
-
- if (sysclk_gpio == 0)
- return SYSCLK_66;
- else
- return SYSCLK_100;
-
- return 0;
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
- set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
- set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- puts("\nSecond program loader running in sram...");
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
deleted file mode 100644
index 73f5729..0000000
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#ifndef CONFIG_SPL_BUILD
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_16M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-
-#endif /* #if defined(CONFIG_PCI) */
-#endif
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
- /* *I*G - VSC7385 Switch */
- SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
-
-#ifdef CONFIG_SYS_INIT_L2_ADDR
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
- 0, 11, BOOKE_PAGESZ_256K, 1),
-#if CONFIG_SYS_L2_SIZE >= (256 << 10)
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 12, BOOKE_PAGESZ_256K, 1),
-#endif
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_1G, 1)
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020come/Kconfig b/board/freescale/p2020come/Kconfig
deleted file mode 100644
index 8ce5cf1..0000000
--- a/board/freescale/p2020come/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020COME
-
-config SYS_BOARD
- default "p2020come"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020COME"
-
-endif
diff --git a/board/freescale/p2020come/MAINTAINERS b/board/freescale/p2020come/MAINTAINERS
deleted file mode 100644
index ab3ef94..0000000
--- a/board/freescale/p2020come/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-P2020COME BOARD
-M: Ira W. Snyder <iws@ovro.caltech.edu>
-S: Maintained
-F: board/freescale/p2020come/
-F: include/configs/P2020COME.h
-F: configs/P2020COME_SDCARD_defconfig
-F: configs/P2020COME_SPIFLASH_defconfig
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
deleted file mode 100644
index 4857136..0000000
--- a/board/freescale/p2020come/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020come.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
deleted file mode 100644
index b642e12..0000000
--- a/board/freescale/p2020come/ddr.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2009, 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
-
- if (!pdimm->n_ranks)
- return;
-
- /*
- * Set DDR_SDRAM_CLK_CNTL = 0x02800000
- *
- * Clock is launched 5/8 applied cycle after address/command
- */
- popts->clk_adjust = 5;
-}
diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
deleted file mode 100644
index 7048a08..0000000
--- a/board/freescale/p2020come/law.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * Create a dummy LAW entry for the DDR SDRAM which will be replaced when
- * the DDR SPD setup code runs.
- *
- * This table would be empty, except that it is used before the BSS section is
- * initialized, and therefore must have at least one entry to push it into
- * the DATA section.
- */
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
deleted file mode 100644
index 1db37e3..0000000
--- a/board/freescale/p2020come/p2020come.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * Copyright 2009,2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/mpc85xx_gpio.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <vsc7385.h>
-#include <netdev.h>
-#include <mmc.h>
-#include <malloc.h>
-#include <i2c.h>
-
-#if defined(CONFIG_PCI)
-#include <asm/fsl_pci.h>
-#include <pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PCI)
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-
-void ft_pci_board_setup(void *blob)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
-
-#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
- SGMII_PHY_RST_SET | PCIE_RST_SET | \
- RGMII_PHY_RST_SET)
-
-#define SYSCLK_MASK 0x00200000
-#define BOARDREV_MASK 0x10100000
-#define BOARDREV_B 0x10100000
-#define BOARDREV_C 0x00100000
-#define BOARDREV_D 0x00000000
-
-#define SYSCLK_66 66666666
-#define SYSCLK_50 50000000
-#define SYSCLK_100 100000000
-
-unsigned long get_board_sys_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- return SYSCLK_66;
- case 0x0A:
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-unsigned long get_board_ddr_clk(ulong dummy)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
-
- ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
- switch (ddr_ratio) {
- case 0x0C:
- case 0x0A:
- return SYSCLK_66;
- case 0x08:
- return SYSCLK_100;
- default:
- puts("ERROR: unknown DDR ratio\n");
- return SYSCLK_100;
- }
-}
-
-#ifdef CONFIG_MMC
-int board_early_init_f(void)
-{
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-
- /* All the device are enable except for SRIO12 */
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
- return 0;
-}
-#endif
-
-#define GPIO_DIR 0x0f3a0000
-#define GPIO_ODR 0x00000000
-#define GPIO_DAT 0x001a0000
-
-int checkboard(void)
-{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
-
- /*
- * GPIO
- * 0 - 3: CarryBoard Input;
- * 4 - 7: CarryBoard Output;
- * 8 : Mux as SDHC_CD (card detection)
- * 9 : Mux as SDHC_WP
- * 10 : Clear Watchdog timer
- * 11 : LED Input
- * 12 : Output to 1
- * 13 : Open Drain
- * 14 : LED Output
- * 15 : Switch Input
- *
- * Set GPIOs 11, 12, 14 to 1.
- */
- out_be32(&pgpio->gpodr, GPIO_ODR);
- mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
-
- puts("Board: Freescale COM Express P2020\n");
- return 0;
-}
-
-#define M41ST85W_I2C_BUS 1
-#define M41ST85W_I2C_ADDR 0x68
-#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
-
-static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
-{
- u8 data;
-
- if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to read %s bit\n", name);
- return;
- }
-
- if (data & mask) {
- data &= ~mask;
- if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
- M41ST85W_ERROR("unable to clear %s bit\n", name);
- return;
- }
- }
-}
-
-#define M41ST85W_REG_SEC2 0x01
-#define M41ST85W_REG_SEC2_ST 0x80
-
-#define M41ST85W_REG_ALHOUR 0x0c
-#define M41ST85W_REG_ALHOUR_HT 0x40
-
-/*
- * The P2020COME board has a STMicro M41ST85W RTC/watchdog
- * at i2c bus 1 address 0x68.
- */
-static void start_rtc(void)
-{
- unsigned int bus = i2c_get_bus_num();
-
- if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
- M41ST85W_ERROR("unable to set i2c bus\n");
- goto out;
- }
-
- /* ensure ST (stop) and HT (halt update) bits are cleared */
- m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
- m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
-
-out:
- /* reset the i2c bus */
- i2c_set_bus_num(bus);
-}
-
-int board_early_init_r(void)
-{
- start_rtc();
- return 0;
-}
-
-#define M41ST85W_REG_WATCHDOG 0x09
-#define M41ST85W_REG_WATCHDOG_WDS 0x80
-#define M41ST85W_REG_WATCHDOG_BMB0 0x04
-
-void board_reset(void)
-{
- u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
-
- /* set the hardware watchdog timeout to 1/16 second, then hang */
- i2c_set_bus_num(M41ST85W_I2C_BUS);
- i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
-
- while (1)
- /* hang */;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
- if (!num) {
- printf("No TSECs initialized\n");
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
-#if defined(CONFIG_PCI)
- ft_pci_board_setup(blob);
-#endif
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
deleted file mode 100644
index 08a1e34..0000000
--- a/board/freescale/p2020come/tlb.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-#if defined(CONFIG_PCI)
- /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
- CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- /*
- * *I*G* - PCI I/O
- *
- * PCI3 => 0xFFC10000
- * PCI2 => 0xFFC2,0000
- * PCI1 => 0xFFC3,0000
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
-#endif /* #if defined(CONFIG_PCI) */
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/Kconfig b/board/freescale/p2020ds/Kconfig
deleted file mode 100644
index e527ec9..0000000
--- a/board/freescale/p2020ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_P2020DS
-
-config SYS_BOARD
- default "p2020ds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "P2020DS"
-
-endif
diff --git a/board/freescale/p2020ds/MAINTAINERS b/board/freescale/p2020ds/MAINTAINERS
deleted file mode 100644
index cb61fc5..0000000
--- a/board/freescale/p2020ds/MAINTAINERS
+++ /dev/null
@@ -1,10 +0,0 @@
-P2020DS BOARD
-#M: -
-S: Maintained
-F: board/freescale/p2020ds/
-F: include/configs/P2020DS.h
-F: configs/P2020DS_defconfig
-F: configs/P2020DS_36BIT_defconfig
-F: configs/P2020DS_DDR2_defconfig
-F: configs/P2020DS_SDCARD_defconfig
-F: configs/P2020DS_SPIFLASH_defconfig
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
deleted file mode 100644
index ee00806..0000000
--- a/board/freescale/p2020ds/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2007-2009 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += p2020ds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
deleted file mode 100644
index debe70b..0000000
--- a/board/freescale/p2020ds/ddr.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-struct board_specific_parameters {
- u32 n_ranks;
- u32 datarate_mhz_high;
- u32 clk_adjust;
- u32 cpo;
- u32 write_data_delay;
- u32 force_2t;
-};
-
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- *
- * ranges for parameters:
- * wr_data_delay = 0-6
- * clk adjust = 0-8
- * cpo 2-0x1E (30)
- */
-static const struct board_specific_parameters dimm0[] = {
- /*
- * memory controller 0
- * num| hi| clk| cpo|wrdata|2T
- * ranks| mhz|adjst| | delay|
- */
-#ifdef CONFIG_SYS_FSL_DDR2
- {2, 549, 4, 0x1f, 2, 0},
- {2, 680, 4, 0x1f, 3, 0},
- {2, 850, 4, 0x1f, 4, 0},
- {1, 549, 4, 0x1f, 2, 0},
- {1, 680, 4, 0x1f, 3, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#else
- {2, 850, 6, 0x1f, 4, 0},
- {1, 850, 4, 0x1f, 4, 0},
-#endif
- {}
-};
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
- ulong ddr_freq;
- int i;
-
- if (ctrl_num) {
- printf("Wrong parameter for controller number %d", ctrl_num);
- return;
- }
- if (!pdimm->n_ranks)
- return;
-
- /*
- * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
- * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
- * there are two dimms in the controller, set odt_rd_cfg to 3 and
- * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
- */
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- popts->cs_local_opts[i].odt_rd_cfg = 0;
- popts->cs_local_opts[i].odt_wr_cfg = 1;
- }
-
- pbsp = dimm0;
-
- /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
- * freqency and n_banks specified in board_specific_parameters table.
- */
- ddr_freq = get_ddr_freq(0) / 1000000;
- while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
- if (ddr_freq <= pbsp->datarate_mhz_high) {
- popts->clk_adjust = pbsp->clk_adjust;
- popts->cpo_override = pbsp->cpo;
- popts->write_data_delay =
- pbsp->write_data_delay;
- popts->twot_en = pbsp->force_2t;
- goto found;
- }
- pbsp_highest = pbsp;
- }
- pbsp++;
- }
-
- if (pbsp_highest) {
- printf("Error: board specific timing not found "
- "for data rate %lu MT/s!\n"
- "Trying to use the highest speed (%u) parameters\n",
- ddr_freq, pbsp_highest->datarate_mhz_high);
- popts->clk_adjust = pbsp_highest->clk_adjust;
- popts->cpo_override = pbsp_highest->cpo;
- popts->write_data_delay = pbsp_highest->write_data_delay;
- popts->twot_en = pbsp_highest->force_2t;
- } else {
- panic("DIMM is not supported by this board");
- }
-
-found:
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
- popts->wrlvl_en = 1;
- /* Write leveling override */
- popts->wrlvl_override = 1;
- popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x8;
- /* Rtt and Rtt_WR override */
- popts->rtt_override = 1;
- popts->rtt_override_value = DDR3_RTT_120_OHM;
- popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
-}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
deleted file mode 100644
index 9cd4da9..0000000
--- a/board/freescale/p2020ds/law.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
deleted file mode 100644
index 5d18e8d..0000000
--- a/board/freescale/p2020ds/p2020ds.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <asm/fsl_law.h>
-#include <netdev.h>
-
-#include "../common/ngpixis.h"
-#include "../common/sgmii_riser.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_MMC
- ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD |
- MPC85xx_PMUXCR_SDHC_WP));
-#endif
-
- return 0;
-}
-
-int checkboard(void)
-{
- u8 sw;
-
- printf("Board: P2020DS Sys ID: 0x%02x, "
- "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
-
- sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
- sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
-
- if (sw < 0x8)
- /* The lower two bits are the actual vbank number */
- printf("vBank: %d\n", sw & 3);
- else
- puts("Promjet\n");
-
- return 0;
-}
-
-#if !defined(CONFIG_DDR_SPD)
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-
-phys_size_t fixed_sdram(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
- uint d_init;
-
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
- ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
- ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
- ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
- ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
- ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
- ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
- ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
- ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
- ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
-
- if (!strcmp("performance", getenv("perf_mode"))) {
- /* Performance Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
- } else {
- /* Stable Mode Values */
-
- ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-
- /* ECC will be assumed in stable mode */
- ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
- ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
- ddr->err_sbe = CONFIG_SYS_DDR_SBE;
-
- asm("sync;isync");
-
- udelay(500);
-
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- }
-
-#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- d_init = 1;
- debug("DDR - 1st controller: memory initializing\n");
- /*
- * Poll until memory is initialized.
- * 512 Meg at 400 might hit this 200 times or so.
- */
- while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
- udelay(1000);
- debug("DDR: memory initialized\n\n");
- asm("sync; isync");
- udelay(500);
-#endif
-
- if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
- LAW_TRGT_IF_DDR) < 0) {
- printf("ERROR setting Local Access Windows for DDR\n");
- return 0;
- };
-
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-
-#endif
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
- fsl_pcie_init_board(0);
-}
-#endif
-
-int board_early_init_r(void)
-{
- const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
- int flash_esel = find_tlb_idx((void *)flashbase, 1);
-
- /*
- * Remap Boot flash + PROMJET region to caching-inhibited
- * so that flash can be erased properly.
- */
-
- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
-
- if (flash_esel == -1) {
- /* very unlikely unless something is messed up */
- puts("Error: Could not find TLB for FLASH BASE\n");
- flash_esel = 2; /* give our best effort to continue */
- } else {
- /* invalidate existing TLB entry for flash + promjet */
- disable_tlb(flash_esel);
- }
-
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, flash_esel, BOOKE_PAGESZ_256M, 1);
-
- return 0;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- if (is_serdes_configured(SGMII_TSEC2)) {
- puts("eTSEC2 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
- }
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (is_serdes_configured(SGMII_TSEC3)) {
- puts("eTSEC3 is in sgmii mode.\n");
- tsec_info[num].flags |= TSEC_SGMII;
-}
- num++;
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_init(tsec_info, num);
-#endif
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
-
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- phys_addr_t base;
- phys_size_t size;
-
- ft_cpu_setup(blob, bd);
-
- base = getenv_bootm_low();
- size = getenv_bootm_size();
-
- fdt_fixup_memory(blob, (u64)base, (u64)size);
-
-#ifdef CONFIG_HAS_FSL_DR_USB
- fdt_fixup_dr_usb(blob, bd);
-#endif
-
- FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
- fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
deleted file mode 100644
index 02da6e8..0000000
--- a/board/freescale/p2020ds/tlb.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 1),
-
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /* W**G* - Flash/promjet, localbus */
- /* This will be changed to *I*G* after relocation to RAM. */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
-
- /* *I*G* - PCI */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
- CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-
- /* *I*G* - PCI I/O */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_256K, 1),
-
- /* *I*G - NAND */
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
-
- SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4K, 1),
-
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- /* *I*G - L2SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_256K, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
- CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_256K, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 46fc64e..2d4d10f 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -152,6 +153,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -166,5 +180,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index f3141b5..708afca 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -19,10 +19,10 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -242,6 +242,16 @@ void board_retimer_ds125df111_init(void)
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -395,14 +405,3 @@ void qixis_dump_switch(void)
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t102xrdb/cpld.h b/board/freescale/t102xrdb/cpld.h
index 5a3100f..db50f81 100644
--- a/board/freescale/t102xrdb/cpld.h
+++ b/board/freescale/t102xrdb/cpld.h
@@ -43,3 +43,7 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80
+
+#define CPLD_PCIE_SGMII_MUX 0x80
+#define CPLD_OVERRIDE_BOOT_EN 0x01
+#define CPLD_OVERRIDE_MUX_EN 0x02 /* PCIE/2.5G-SGMII mux override enable */
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index a20330b..a2a8f4c 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -136,6 +137,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -150,5 +164,10 @@ phys_size_t initdram(int board_type)
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 2e400c4..f611ff0 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,6 +21,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
+#include "../common/fman.h"
int board_eth_init(bd_t *bis)
{
@@ -51,15 +52,22 @@ int board_eth_init(bd_t *bis)
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
- /* Set the two on-board RGMII PHY address */
- fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+ /* Set the on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0x95:
- /* 10G XFI with Aquantia PHY */
+ /* set the on-board RGMII2 PHY */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
+
+ /* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
+ case 0x77:
+ case 0x135:
+ /* set the on-board 2.5G SGMII AQR105 PHY */
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+ break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1);
@@ -73,6 +81,10 @@ int board_eth_init(bd_t *bis)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+ fm_info_set_mdio(i, dev);
+ break;
default:
break;
}
@@ -95,6 +107,18 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
+ (port == FM1_DTSEC3)) {
+ fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
+ fdt_setprop(fdt, offset, "phy-connection-type",
+ "sgmii-2500", 10);
+ fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
+ }
+}
+
void fdt_fixup_board_enet(void *fdt)
{
}
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index dd2dec4..1a3a996 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -11,6 +11,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,12 @@ void board_init_f(ulong bootflag)
console_init_f();
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f5c438d..e196f12 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -16,10 +16,10 @@
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
-#include <asm/mpc85xx_gpio.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#include "cpld.h"
+#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -27,6 +27,11 @@ int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
@@ -50,7 +55,40 @@ int checkboard(void)
#endif
puts("SERDES Reference Clocks:\n");
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ if (srds_s1 == 0x95)
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
+ else
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+
+ return 0;
+}
+
+static void board_mux_lane(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1;
+ u8 reg = CPLD_READ(misc_ctl_status);
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (srds_prtcl_s1 == 0x95) {
+ /* Route Lane B to PCIE */
+ CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
+ } else {
+ /* Route Lane B to SGMII */
+ CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
+ }
+ CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
+}
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
return 0;
}
@@ -86,6 +124,7 @@ int board_early_init_r(void)
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+ board_mux_lane();
return 0;
}
@@ -131,14 +170,3 @@ int ft_board_setup(void *blob, bd_t *bd)
return 0;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 43f952f..8240240 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -11,6 +11,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -100,6 +101,19 @@ found:
#endif
}
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+ void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(qixis_base + 0x21, 0x2);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
+
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
@@ -112,5 +126,10 @@ phys_size_t initdram(int board_type)
dram_size *= 0x100000;
puts(" DDR: ");
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+ fsl_dp_resume();
+#endif
+
return dram_size;
}
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 06d9086..8c82934 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -18,6 +18,7 @@
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
#include "../common/fman.h"
#include "../common/qixis.h"
@@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void)
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
+ lane_to_slot[6] = 7;
lane_to_slot[7] = 7;
break;
case 0x8d:
@@ -438,6 +440,12 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
+#ifdef CONFIG_VSC9953
+ int lane;
+ int phy_addr;
+ phy_interface_t phy_int;
+ struct mii_dev *bus;
+#endif
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
@@ -477,6 +485,7 @@ int board_eth_init(bd_t *bis)
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
+ fm_info_set_mdio(i, NULL);
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
@@ -491,6 +500,90 @@ int board_eth_init(bd_t *bis)
}
}
+#ifdef CONFIG_VSC9953
+ for (i = 0; i < VSC9953_MAX_PORTS; i++) {
+ lane = -1;
+ phy_addr = 0;
+ phy_int = PHY_INTERFACE_MODE_NONE;
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
+ /* PHYs connected over QSGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
+ i;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+ break;
+ }
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_SW1_MAC1 + i);
+
+ if (lane < 0)
+ break;
+
+ /* PHYs connected over QSGMII */
+ if (i != 3 || lane_to_slot[lane] == 7)
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ + i;
+ else
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
+ phy_int = PHY_INTERFACE_MODE_SGMII;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
+ /* PHYs connected over QSGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
+ i - 4;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+ break;
+ }
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_SW1_MAC1 + i);
+ /* PHYs connected over SGMII */
+ if (lane >= 0) {
+ phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ + i - 3;
+ phy_int = PHY_INTERFACE_MODE_SGMII;
+ }
+ break;
+ case 8:
+ if (serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1) < 0)
+ /* FM1@DTSEC1 is connected to SW1@PORT8 */
+ vsc9953_port_enable(i);
+ break;
+ case 9:
+ if (serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC2) < 0) {
+ /* Enable L2 On MAC2 using SCFG */
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+ CONFIG_SYS_MPC85xx_SCFG;
+
+ out_be32(&scfg->esgmiiselcr,
+ in_be32(&scfg->esgmiiselcr) |
+ (0x80000000));
+ vsc9953_port_enable(i);
+ }
+ break;
+ }
+
+ if (lane >= 0) {
+ bus = mii_dev_for_muxval(lane_to_slot[lane]);
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_enable(i);
+ }
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ }
+
+#endif
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index 13285be..eaca57f 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -19,8 +19,8 @@
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
-#include <asm/mpc85xx_gpio.h>
+#include "../common/sleep.h"
#include "../common/qixis.h"
#include "t1040qds.h"
#include "t1040qds_qixis.h"
@@ -115,6 +115,16 @@ static void qe_board_setup(void)
}
}
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+ if (is_warm_boot())
+ fsl_dp_disable_console();
+#endif
+
+ return 0;
+}
+
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
@@ -281,14 +291,3 @@ int board_need_mem_reset(void)
{
return 1;
}
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
- /* does not provide HW signals for power management */
- QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
- /* Disable MCKE isolation */
- gpio_set_value(2, 0);
- udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index b61e1c0..13d9be9 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -21,3 +21,4 @@ T1040RDB_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/T1040RDB_SECURE_BOOT_defconfig
+F: configs/T1042RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index c8b6c67..7581a4cd 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -6,11 +6,13 @@
#include <common.h>
#include <netdev.h>
+#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
+#include <vsc9953.h>
#include "../common/fman.h"
@@ -20,6 +22,11 @@ int board_eth_init(bd_t *bis)
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
+#ifdef CONFIG_VSC9953
+ phy_interface_t phy_int;
+ struct mii_dev *bus;
+#endif
+
printf("Initializing Fman\n");
memac_mdio_info.regs =
@@ -72,10 +79,58 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(i, 0);
break;
}
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
+ fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+ fm_info_set_mdio(i, NULL);
+ else
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(
+ DEFAULT_FM_MDIO_NAME));
+ }
+
+#ifdef CONFIG_VSC9953
+ /* SerDes configured for QSGMII */
+ if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
+ for (i = 0; i < 4; i++) {
+ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ vsc9953_port_enable(i);
+ }
+ }
+ if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
+ for (i = 4; i < 8; i++) {
+ bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+ phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
+ phy_int = PHY_INTERFACE_MODE_QSGMII;
+
+ vsc9953_port_info_set_mdio(i, bus);
+ vsc9953_port_info_set_phy_address(i, phy_addr);
+ vsc9953_port_info_set_phy_int(i, phy_int);
+ vsc9953_port_enable(i);
+ }
}
+ /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
+ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
+ vsc9953_port_enable(8);
+
+ /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
+ if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
+ /* Enable L2 On MAC2 using SCFG */
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)
+ CONFIG_SYS_MPC85xx_SCFG;
+
+ out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
+ (0x80000000));
+ vsc9953_port_enable(9);
+ }
+#endif
+
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index 142c6a8..879bd1a 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -101,7 +101,7 @@ int board_eth_init(bd_t *bis)
}
#if (CONFIG_SYS_NUM_FMAN == 2)
- if (srds_prtcl_s2 == 56) {
+ if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index fdbbe5e..e46c7b2 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 27_56_1_9
+#serdes protocol 27_55_1_9
16070019 18101916 00000000 00000000
-6c700848 00448c00 6c020000 f5000000
+6c6e0848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028