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authorMarkus Klotzbuecher <mk@denx.de>2008-01-09 13:57:10 +0100
committerMarkus Klotzbuecher <mk@denx.de>2008-01-09 13:57:10 +0100
commit6a40ef62c4300e9f606deef0a4618cbc4b514a51 (patch)
treec01bdd0e773d092f13af05567fa92fb9072df9e0 /board/freescale
parent245a362ad3c0c1b84fccc9fec7b623eb14f6e502 (diff)
parent07eb02687f008721974a2fb54cd7fdc28033ab3c (diff)
downloadu-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.zip
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Merge git://www.denx.de/git/u-boot
Conflicts: board/tqm5200/tqm5200.c
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/common/Makefile4
-rw-r--r--board/freescale/common/cadmus.c95
-rw-r--r--board/freescale/common/cadmus.h54
-rw-r--r--board/freescale/common/eeprom.c60
-rw-r--r--board/freescale/common/eeprom.h50
-rw-r--r--board/freescale/common/fsl_diu_fb.c618
-rw-r--r--board/freescale/common/fsl_diu_fb.h69
-rw-r--r--board/freescale/common/fsl_logo_bmp.c878
-rw-r--r--board/freescale/common/ft_board.c72
-rw-r--r--board/freescale/common/pixis.c5
-rw-r--r--board/freescale/common/via.c109
-rw-r--r--board/freescale/common/via.h18
-rw-r--r--board/freescale/m54455evb/config.mk4
-rw-r--r--board/freescale/m54455evb/u-boot.atm144
-rw-r--r--board/freescale/m54455evb/u-boot.int141
-rw-r--r--board/freescale/mpc8313erdb/mpc8313erdb.c14
-rw-r--r--board/freescale/mpc8323erdb/mpc8323erdb.c10
-rw-r--r--board/freescale/mpc832xemds/mpc832xemds.c14
-rw-r--r--board/freescale/mpc832xemds/pci.c46
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c14
-rw-r--r--board/freescale/mpc8349emds/pci.c76
-rw-r--r--board/freescale/mpc8349itx/mpc8349itx.c14
-rw-r--r--board/freescale/mpc8349itx/pci.c76
-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c61
-rw-r--r--board/freescale/mpc8360emds/pci.c46
-rw-r--r--board/freescale/mpc837xemds/Makefile50
-rw-r--r--board/freescale/mpc837xemds/config.mk28
-rw-r--r--board/freescale/mpc837xemds/mpc837xemds.c132
-rw-r--r--board/freescale/mpc837xemds/pci.c65
-rw-r--r--board/freescale/mpc8540ads/Makefile52
-rw-r--r--board/freescale/mpc8540ads/config.mk33
-rw-r--r--board/freescale/mpc8540ads/init.S280
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c348
-rw-r--r--board/freescale/mpc8540ads/u-boot.lds150
-rw-r--r--board/freescale/mpc8541cds/Makefile60
-rw-r--r--board/freescale/mpc8541cds/config.mk30
-rw-r--r--board/freescale/mpc8541cds/init.S255
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c534
-rw-r--r--board/freescale/mpc8541cds/u-boot.lds150
-rw-r--r--board/freescale/mpc8544ds/init.S25
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c83
-rw-r--r--board/freescale/mpc8548cds/Makefile60
-rw-r--r--board/freescale/mpc8548cds/config.mk32
-rw-r--r--board/freescale/mpc8548cds/init.S263
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c547
-rw-r--r--board/freescale/mpc8548cds/u-boot.lds149
-rw-r--r--board/freescale/mpc8555cds/Makefile60
-rw-r--r--board/freescale/mpc8555cds/config.mk30
-rw-r--r--board/freescale/mpc8555cds/init.S255
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c534
-rw-r--r--board/freescale/mpc8555cds/u-boot.lds150
-rw-r--r--board/freescale/mpc8560ads/Makefile52
-rw-r--r--board/freescale/mpc8560ads/config.mk32
-rw-r--r--board/freescale/mpc8560ads/init.S280
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c566
-rw-r--r--board/freescale/mpc8560ads/u-boot.lds153
-rw-r--r--board/freescale/mpc8568mds/Makefile56
-rw-r--r--board/freescale/mpc8568mds/bcsr.c56
-rw-r--r--board/freescale/mpc8568mds/bcsr.h100
-rw-r--r--board/freescale/mpc8568mds/config.mk30
-rw-r--r--board/freescale/mpc8568mds/init.S244
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c555
-rw-r--r--board/freescale/mpc8568mds/u-boot.lds152
-rw-r--r--board/freescale/mpc8610hpcd/Makefile59
-rw-r--r--board/freescale/mpc8610hpcd/config.mk25
-rw-r--r--board/freescale/mpc8610hpcd/init.S147
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c546
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c177
-rw-r--r--board/freescale/mpc8610hpcd/u-boot.lds135
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c60
70 files changed, 10152 insertions, 320 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 44f613e..9cee9f1 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -31,7 +31,9 @@ LIB = $(obj)lib$(VENDOR).a
COBJS := sys_eeprom.o \
pixis.o \
- pq-mds-pib.o
+ pq-mds-pib.o \
+ fsl_logo_bmp.o \
+ fsl_diu_fb.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
new file mode 100644
index 0000000..5f86de5
--- /dev/null
+++ b/board/freescale/common/cadmus.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+
+
+/*
+ * CADMUS Board System Registers
+ */
+#ifndef CFG_CADMUS_BASE_REG
+#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000)
+#endif
+
+typedef struct cadmus_reg {
+ u_char cm_ver; /* Board version */
+ u_char cm_csr; /* General control/status */
+ u_char cm_rst; /* Reset control */
+ u_char cm_hsclk; /* High speed clock */
+ u_char cm_hsxclk; /* High speed clock extended */
+ u_char cm_led; /* LED data */
+ u_char cm_pci; /* PCI control/status */
+ u_char cm_dma; /* DMA control */
+ u_char cm_reserved[248]; /* Total 256 bytes */
+} cadmus_reg_t;
+
+
+unsigned int
+get_board_version(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ return cadmus->cm_ver;
+}
+
+
+unsigned long
+get_clock_freq(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
+
+ if (pci1_speed == 0) {
+ return 33000000;
+ } else if (pci1_speed == 1) {
+ return 66000000;
+ } else {
+ /* Really, unknown. Be safe? */
+ return 33000000;
+ }
+}
+
+
+unsigned int
+get_pci_slot(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ /*
+ * PCI slot in USER bits CSR[6:7] by convention.
+ */
+ return ((cadmus->cm_csr >> 6) & 0x3) + 1;
+}
+
+
+unsigned int
+get_pci_dual(void)
+{
+ volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+
+ /*
+ * PCI DUAL in CM_PCI[3]
+ */
+ return cadmus->cm_pci & 0x10;
+}
diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h
new file mode 100644
index 0000000..217ea64
--- /dev/null
+++ b/board/freescale/common/cadmus.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CADMUS_H_
+#define __CADMUS_H_
+
+
+/*
+ * CADMUS Board System Register interface.
+ */
+
+/*
+ * Returns board version register.
+ */
+extern unsigned int get_board_version(void);
+
+/*
+ * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
+ */
+extern unsigned long get_clock_freq(void);
+
+
+/*
+ * Returns 1 - 4, as found in the USER CSR[6:7] bits.
+ */
+extern unsigned int get_pci_slot(void);
+
+
+/*
+ * Returns PCI DUAL as found in CM_PCI[3].
+ */
+extern unsigned int get_pci_dual(void);
+
+
+#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/eeprom.c b/board/freescale/common/eeprom.c
new file mode 100644
index 0000000..5034e0c
--- /dev/null
+++ b/board/freescale/common/eeprom.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <i2c.h>
+
+#include "eeprom.h"
+
+
+typedef struct {
+ char idee_pcbid[4]; /* "CCID" for CDC v1.X */
+ u8 idee_major;
+ u8 idee_minor;
+ char idee_serial[10];
+ char idee_errata[2];
+ char idee_date[8]; /* yyyymmdd */
+ /* The rest of the EEPROM space is reserved */
+} id_eeprom_t;
+
+
+unsigned int
+get_cpu_board_revision(void)
+{
+ uint major = 0;
+ uint minor = 0;
+
+ id_eeprom_t id_eeprom;
+
+ i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2,
+ (uchar *) &id_eeprom, sizeof(id_eeprom));
+
+ major = id_eeprom.idee_major;
+ minor = id_eeprom.idee_minor;
+
+ if (major == 0xff && minor == 0xff) {
+ major = minor = 0;
+ }
+
+ return MPC85XX_CPU_BOARD_REV(major,minor);
+}
diff --git a/board/freescale/common/eeprom.h b/board/freescale/common/eeprom.h
new file mode 100644
index 0000000..12a0789
--- /dev/null
+++ b/board/freescale/common/eeprom.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EEPROM_H_
+#define __EEPROM_H_
+
+
+/*
+ * EEPROM Board System Register interface.
+ */
+
+
+/*
+ * CPU Board Revision
+ */
+#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff))
+#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff)
+#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff)
+
+#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0)
+#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0)
+#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1)
+
+/*
+ * Returns CPU board revision register as a 16-bit value with
+ * the Major in the high byte, and Minor in the low byte.
+ */
+extern unsigned int get_cpu_board_revision(void);
+
+
+#endif /* __CADMUS_H_ */
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
new file mode 100644
index 0000000..5a8576e
--- /dev/null
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -0,0 +1,618 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <malloc.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "fsl_diu_fb.h"
+
+#ifdef DEBUG
+#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args)
+#else
+#define DPRINTF(fmt, args...)
+#endif
+
+struct fb_videomode {
+ const char *name; /* optional */
+ unsigned int refresh; /* optional */
+ unsigned int xres;
+ unsigned int yres;
+ unsigned int pixclock;
+ unsigned int left_margin;
+ unsigned int right_margin;
+ unsigned int upper_margin;
+ unsigned int lower_margin;
+ unsigned int hsync_len;
+ unsigned int vsync_len;
+ unsigned int sync;
+ unsigned int vmode;
+ unsigned int flag;
+};
+
+#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
+#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
+#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+
+/*
+ * These parameters give default parameters
+ * for video output 1024x768,
+ * FIXME - change timing to proper amounts
+ * hsync 31.5kHz, vsync 60Hz
+ */
+static struct fb_videomode fsl_diu_mode_1024 = {
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode fsl_diu_mode_1280 = {
+ .name = "1280x1024-60",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 1024,
+ .pixclock = 9375,
+ .left_margin = 38,
+ .right_margin = 128,
+ .upper_margin = 2,
+ .lower_margin = 7,
+ .hsync_len = 216,
+ .vsync_len = 37,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+/*
+ * These are the fields of area descriptor(in DDR memory) for every plane
+ */
+struct diu_ad {
+ /* Word 0(32-bit) in DDR memory */
+ unsigned int pix_fmt; /* hard coding pixel format */
+ /* Word 1(32-bit) in DDR memory */
+ unsigned int addr;
+ /* Word 2(32-bit) in DDR memory */
+ unsigned int src_size_g_alpha;
+ /* Word 3(32-bit) in DDR memory */
+ unsigned int aoi_size;
+ /* Word 4(32-bit) in DDR memory */
+ unsigned int offset_xyi;
+ /* Word 5(32-bit) in DDR memory */
+ unsigned int offset_xyd;
+ /* Word 6(32-bit) in DDR memory */
+ unsigned int ckmax_r:8;
+ unsigned int ckmax_g:8;
+ unsigned int ckmax_b:8;
+ unsigned int res9:8;
+ /* Word 7(32-bit) in DDR memory */
+ unsigned int ckmin_r:8;
+ unsigned int ckmin_g:8;
+ unsigned int ckmin_b:8;
+ unsigned int res10:8;
+ /* Word 8(32-bit) in DDR memory */
+ unsigned int next_ad;
+ /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
+ unsigned int res1;
+ unsigned int res2;
+ unsigned int res3;
+}__attribute__ ((packed));
+
+/*
+ * DIU register map
+ */
+struct diu {
+ unsigned int desc[3];
+ unsigned int gamma;
+ unsigned int pallete;
+ unsigned int cursor;
+ unsigned int curs_pos;
+ unsigned int diu_mode;
+ unsigned int bgnd;
+ unsigned int bgnd_wb;
+ unsigned int disp_size;
+ unsigned int wb_size;
+ unsigned int wb_mem_addr;
+ unsigned int hsyn_para;
+ unsigned int vsyn_para;
+ unsigned int syn_pol;
+ unsigned int thresholds;
+ unsigned int int_status;
+ unsigned int int_mask;
+ unsigned int colorbar[8];
+ unsigned int filling;
+ unsigned int plut;
+} __attribute__ ((packed));
+
+struct diu_hw {
+ struct diu *diu_reg;
+ volatile unsigned int mode; /* DIU operation mode */
+};
+
+struct diu_addr {
+ unsigned char * paddr; /* Virtual address */
+ unsigned int offset;
+};
+
+#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */
+
+/*
+ * Modes of operation of DIU
+ */
+#define MFB_MODE0 0 /* DIU off */
+#define MFB_MODE1 1 /* All three planes output to display */
+#define MFB_MODE2 2 /* Plane 1 to display,
+ * planes 2+3 written back to memory */
+#define MFB_MODE3 3 /* All three planes written back to memory */
+#define MFB_MODE4 4 /* Color bar generation */
+
+#define MAX_CURS 32
+
+static struct fb_info fsl_fb_info;
+static struct diu_addr gamma, cursor;
+static struct diu_ad fsl_diu_fb_ad __attribute__ ((aligned(32)));
+static struct diu_ad dummy_ad __attribute__ ((aligned(32)));
+static unsigned char *dummy_fb;
+static struct diu_hw dr = {
+ .mode = MFB_MODE1,
+};
+
+int fb_enabled = 0;
+int fb_initialized = 0;
+const int default_xres = 1280;
+const int default_pixel_format = 0x88882317;
+
+static int map_video_memory(struct fb_info *info, unsigned long bytes_align);
+static void enable_lcdc(void);
+static void disable_lcdc(void);
+static int fsl_diu_enable_panel(struct fb_info *info);
+static int fsl_diu_disable_panel(struct fb_info *info);
+static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align);
+static u32 get_busfreq(void);
+
+int fsl_diu_init(int xres,
+ unsigned int pixel_format,
+ int gamma_fix,
+ unsigned char *splash_bmp)
+{
+ struct fb_videomode *fsl_diu_mode_db;
+ struct diu_ad *ad = &fsl_diu_fb_ad;
+ struct diu *hw;
+ struct fb_info *info = &fsl_fb_info;
+ struct fb_var_screeninfo *var = &info->var;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
+ unsigned char *gamma_table_base;
+ unsigned int i, j;
+ unsigned long speed_ccb, temp, pixval;
+
+ DPRINTF("Enter fsl_diu_init\n");
+ dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET);
+ hw = (struct diu *) dr.diu_reg;
+
+ disable_lcdc();
+
+ if (xres == 1280) {
+ fsl_diu_mode_db = &fsl_diu_mode_1280;
+ } else {
+ fsl_diu_mode_db = &fsl_diu_mode_1024;
+ }
+
+ if (0 == fb_initialized) {
+ allocate_buf(&gamma, 768, 32);
+ DPRINTF("gamma is allocated @ 0x%x\n",
+ (unsigned int)gamma.paddr);
+ allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32);
+ DPRINTF("curosr is allocated @ 0x%x\n",
+ (unsigned int)cursor.paddr);
+
+ /* create a dummy fb and dummy ad */
+ dummy_fb = malloc(64);
+ if (NULL == dummy_fb) {
+ printf("Cannot allocate dummy fb\n");
+ return -1;
+ }
+ dummy_ad.addr = cpu_to_le32((unsigned int)dummy_fb);
+ dummy_ad.pix_fmt = 0x88882317;
+ dummy_ad.src_size_g_alpha = 0x04400000; /* alpha = 0 */
+ dummy_ad.aoi_size = 0x02000400;
+ dummy_ad.offset_xyi = 0;
+ dummy_ad.offset_xyd = 0;
+ dummy_ad.next_ad = 0;
+ /* Memory allocation for framebuffer */
+ if (map_video_memory(info, 32)) {
+ printf("Unable to allocate fb memory 1\n");
+ return -1;
+ }
+ } else {
+ memset(info->screen_base, 0, info->smem_len);
+ }
+
+ dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
+ dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
+ dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
+ DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
+ DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]);
+
+ /* read mode info */
+ var->xres = fsl_diu_mode_db->xres;
+ var->yres = fsl_diu_mode_db->yres;
+ var->bits_per_pixel = 32;
+ var->pixclock = fsl_diu_mode_db->pixclock;
+ var->left_margin = fsl_diu_mode_db->left_margin;
+ var->right_margin = fsl_diu_mode_db->right_margin;
+ var->upper_margin = fsl_diu_mode_db->upper_margin;
+ var->lower_margin = fsl_diu_mode_db->lower_margin;
+ var->hsync_len = fsl_diu_mode_db->hsync_len;
+ var->vsync_len = fsl_diu_mode_db->vsync_len;
+ var->sync = fsl_diu_mode_db->sync;
+ var->vmode = fsl_diu_mode_db->vmode;
+ info->line_length = var->xres * var->bits_per_pixel / 8;
+ info->logo_size = 0;
+ info->logo_height = 0;
+
+ ad->pix_fmt = pixel_format;
+ ad->addr = cpu_to_le32((unsigned int)info->screen_base);
+ ad->src_size_g_alpha
+ = cpu_to_le32((var->yres << 12) | var->xres);
+ /* fix me. AOI should not be greater than display size */
+ ad->aoi_size = cpu_to_le32(( var->yres << 16) | var->xres);
+ ad->offset_xyi = 0;
+ ad->offset_xyd = 0;
+
+ /* Disable chroma keying function */
+ ad->ckmax_r = 0;
+ ad->ckmax_g = 0;
+ ad->ckmax_b = 0;
+
+ ad->ckmin_r = 255;
+ ad->ckmin_g = 255;
+ ad->ckmin_b = 255;
+
+ gamma_table_base = gamma.paddr;
+ DPRINTF("gamma_table_base is allocated @ 0x%x\n",
+ (unsigned int)gamma_table_base);
+
+ /* Prep for DIU init - gamma table */
+
+ for (i = 0; i <= 2; i++)
+ for (j = 0; j <= 255; j++)
+ *gamma_table_base++ = j;
+
+ if (gamma_fix == 1) { /* fix the gamma */
+ DPRINTF("Fix gamma table\n");
+ gamma_table_base = gamma.paddr;
+ for (i = 0; i < 256*3; i++) {
+ gamma_table_base[i] = (gamma_table_base[i] << 2)
+ | ((gamma_table_base[i] >> 6) & 0x03);
+ }
+ }
+
+ DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw);
+
+ /* Program DIU registers */
+
+ hw->gamma = (unsigned int) gamma.paddr;
+ hw->cursor= (unsigned int) cursor.paddr;
+ hw->bgnd = 0x007F7F7F; /* BGND */
+ hw->bgnd_wb = 0; /* BGND_WB */
+ hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
+ hw->wb_size = 0; /* WB SIZE */
+ hw->wb_mem_addr = 0; /* WB MEM ADDR */
+ hw->hsyn_para = var->left_margin << 22 | /* BP_H */
+ var->hsync_len << 11 | /* PW_H */
+ var->right_margin; /* FP_H */
+ hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
+ var->vsync_len << 11 | /* PW_V */
+ var->lower_margin; /* FP_V */
+
+ /* Pixel Clock configuration */
+ DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq());
+ speed_ccb = get_busfreq();
+
+ DPRINTF("DIU pixclock in ps - %d\n", var->pixclock);
+ temp = 1;
+ temp *= 1000000000;
+ temp /= var->pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ DPRINTF("DIU pixval = %lu\n", pixval);
+
+ hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
+ hw->thresholds = 0x00037800; /* The Thresholds */
+ hw->int_status = 0; /* INTERRUPT STATUS */
+ hw->int_mask = 0; /* INT MASK */
+ hw->plut = 0x01F5F666;
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+ temp = *guts_clkdvdr & 0x2000FFFF;
+ *guts_clkdvdr = temp; /* turn off clock */
+ *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16);
+ DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
+
+ fb_initialized = 1;
+
+ if (splash_bmp) {
+ info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0);
+ info->logo_size = info->logo_height * info->line_length;
+ DPRINTF("logo height %d, logo_size 0x%x\n",
+ info->logo_height,info->logo_size);
+ }
+
+ /* Enable the DIU */
+ fsl_diu_enable_panel(info);
+ enable_lcdc();
+
+ return 0;
+}
+
+char *fsl_fb_open(struct fb_info **info)
+{
+ *info = &fsl_fb_info;
+ return (char *) ((unsigned int)(*info)->screen_base
+ + (*info)->logo_size);
+}
+
+void fsl_diu_close(void)
+{
+ struct fb_info *info = &fsl_fb_info;
+ fsl_diu_disable_panel(info);
+}
+
+static int fsl_diu_enable_panel(struct fb_info *info)
+{
+ struct diu *hw = dr.diu_reg;
+ struct diu_ad *ad = &fsl_diu_fb_ad;
+
+ DPRINTF("Entered: enable_panel\n");
+ if (hw->desc[0] != (unsigned int)ad)
+ hw->desc[0] = (unsigned int)ad;
+ DPRINTF("desc[0] = 0x%x\n", hw->desc[0]);
+ return 0;
+}
+
+static int fsl_diu_disable_panel(struct fb_info *info)
+{
+ struct diu *hw = dr.diu_reg;
+
+ DPRINTF("Entered: disable_panel\n");
+ if (hw->desc[0] != (unsigned int)&dummy_ad)
+ hw->desc[0] = (unsigned int)&dummy_ad;
+ return 0;
+}
+
+static int map_video_memory(struct fb_info *info, unsigned long bytes_align)
+{
+ unsigned long offset;
+ unsigned long mask;
+
+ DPRINTF("Entered: map_video_memory\n");
+ /* allocate maximum 1280*1024 with 32bpp */
+ info->smem_len = 1280 * 4 *1024 + bytes_align;
+ DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len);
+ info->screen_base = malloc(info->smem_len);
+ if (info->screen_base == NULL) {
+ printf("Unable to allocate fb memory\n");
+ return -1;
+ }
+ info->smem_start = (unsigned int) info->screen_base;
+ mask = bytes_align - 1;
+ offset = (unsigned long)info->screen_base & mask;
+ if (offset) {
+ info->screen_base += offset;
+ info->smem_len = info->smem_len - (bytes_align - offset);
+ } else
+ info->smem_len = info->smem_len - bytes_align;
+
+ info->screen_size = info->smem_len;
+
+ DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n",
+ info->smem_start, info->smem_len);
+
+ return 0;
+}
+
+static void enable_lcdc(void)
+{
+ struct diu *hw = dr.diu_reg;
+
+ DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
+ if (!fb_enabled) {
+ hw->diu_mode = dr.mode;
+ fb_enabled++;
+ }
+ DPRINTF("diu_mode = %d\n", hw->diu_mode);
+}
+
+static void disable_lcdc(void)
+{
+ struct diu *hw = dr.diu_reg;
+
+ DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
+ if (fb_enabled) {
+ hw->diu_mode = 0;
+ fb_enabled = 0;
+ }
+}
+
+static u32 get_busfreq(void)
+{
+ u32 fs_busfreq = 0;
+
+ fs_busfreq = get_bus_freq(0);
+ return fs_busfreq;
+}
+
+/*
+ * Align to 64-bit(8-byte), 32-byte, etc.
+ */
+static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
+{
+ u32 offset, ssize;
+ u32 mask;
+
+ DPRINTF("Entered: allocate_buf\n");
+ ssize = size + bytes_align;
+ buf->paddr = malloc(ssize);
+ if (!buf->paddr)
+ return -1;
+
+ memset(buf->paddr, 0, ssize);
+ mask = bytes_align - 1;
+ offset = (u32)buf->paddr & mask;
+ if (offset) {
+ buf->offset = bytes_align - offset;
+ buf->paddr = (unsigned char *) ((u32)buf->paddr + offset);
+ } else
+ buf->offset = 0;
+ return 0;
+}
+
+int fsl_diu_display_bmp(unsigned char *bmp,
+ int xoffset,
+ int yoffset,
+ int transpar)
+{
+ struct fb_info *info = &fsl_fb_info;
+ unsigned char r, g, b;
+ unsigned int *fb_t, val;
+ unsigned char *bitmap;
+ unsigned int palette[256];
+ int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp;
+
+ if (!bmp) {
+ printf("Must supply a bitmap address\n");
+ return 0;
+ }
+
+ raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24);
+ width = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18];
+ height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22];
+ bpp = (bmp[29] << 8) | (bmp[28]);
+ ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24);
+ bitmap = bmp + raster;
+ cpp = info->var.bits_per_pixel / 8;
+
+ DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp);
+ DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap);
+ DPRINTF("width = %d\n", width);
+ DPRINTF("height = %d\n", height);
+ DPRINTF("bpp = %d\n", bpp);
+ DPRINTF("ncolors = %d\n", ncolors);
+
+ DPRINTF("xres = %d\n", info->var.xres);
+ DPRINTF("yres = %d\n", info->var.yres);
+ DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base);
+
+ if (((width+xoffset) > info->var.xres) ||
+ ((height+yoffset) > info->var.yres)) {
+ printf("bitmap is out of range, image too large or too much offset\n");
+ return 0;
+ }
+ if (bpp < 24) {
+ for (i = 0, offset = 54; i < ncolors; i++, offset += 4)
+ palette[i] = (bmp[offset+2] << 16)
+ + (bmp[offset+1] << 8) + bmp[offset];
+ }
+
+ switch (bpp) {
+ case 1:
+ for (y = height - 1; y >= 0; y--) {
+ fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+ for (x = 0; x < width; x += 8) {
+ b = *bitmap++;
+ for (k = 0; k < 8; k++) {
+ if (b & 0x80)
+ *fb_t = palette[1];
+ else
+ *fb_t = palette[0];
+ b = b << 1;
+ }
+ }
+ for (i = (width / 2) % 4; i > 0; i--)
+ bitmap++;
+ }
+ break;
+ case 4:
+ for (y = height - 1; y >= 0; y--) {
+ fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+ for (x = 0; x < width; x += 2) {
+ b = *bitmap++;
+ r = (b >> 4) & 0x0F;
+ g = b & 0x0F;
+ *fb_t++ = palette[r];
+ *fb_t++ = palette[g];
+ }
+ for (i = (width / 2) % 4; i > 0; i--)
+ bitmap++;
+ }
+ break;
+ case 8:
+ for (y = height - 1; y >= 0; y--) {
+ fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+ for (x = 0; x < width; x++) {
+ *fb_t++ = palette[ *bitmap++ ];
+ }
+ for (i = (width / 2) % 4; i > 0; i--)
+ bitmap++;
+ }
+ break;
+ case 24:
+ for (y = height - 1; y >= 0; y--) {
+ fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp);
+ for (x = 0; x < width; x++) {
+ b = *bitmap++;
+ g = *bitmap++;
+ r = *bitmap++;
+ val = (r << 16) + (g << 8) + b;
+ *fb_t++ = val;
+ }
+ for (; (x % 4) != 0; x++) /* 4-byte alignment */
+ bitmap++;
+ }
+ break;
+ }
+
+ return height;
+}
+
+void fsl_diu_clear_screen(void)
+{
+ struct fb_info *info = &fsl_fb_info;
+
+ memset(info->screen_base, 0, info->smem_len);
+}
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h
new file mode 100644
index 0000000..6deba32
--- /dev/null
+++ b/board/freescale/common/fsl_diu_fb.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+struct fb_var_screeninfo {
+ unsigned int xres; /* visible resolution */
+ unsigned int yres;
+
+ unsigned int bits_per_pixel; /* guess what */
+
+ /* Timing: All values in pixclocks, except pixclock (of course) */
+ unsigned int pixclock; /* pixel clock in ps (pico seconds) */
+ unsigned int left_margin; /* time from sync to picture */
+ unsigned int right_margin; /* time from picture to sync */
+ unsigned int upper_margin; /* time from sync to picture */
+ unsigned int lower_margin;
+ unsigned int hsync_len; /* length of horizontal sync */
+ unsigned int vsync_len; /* length of vertical sync */
+ unsigned int sync; /* see FB_SYNC_* */
+ unsigned int vmode; /* see FB_VMODE_* */
+ unsigned int rotate; /* angle we rotate counter clockwise */
+};
+
+struct fb_info {
+ struct fb_var_screeninfo var; /* Current var */
+ unsigned long smem_start; /* Start of frame buffer mem */
+ /* (physical address) */
+ unsigned int smem_len; /* Length of frame buffer mem */
+ unsigned int type; /* see FB_TYPE_* */
+ unsigned int line_length; /* length of a line in bytes */
+
+ char *screen_base;
+ unsigned long screen_size;
+ int logo_height;
+ unsigned int logo_size;
+};
+
+
+extern char *fsl_fb_open(struct fb_info **info);
+extern int fsl_diu_init(int xres,
+ unsigned int pixel_format,
+ int gamma_fix,
+ unsigned char *splash_bmp);
+extern void fsl_diu_clear_screen(void);
+extern int fsl_diu_display_bmp(unsigned char *bmp,
+ int xoffset,
+ int yoffset,
+ int transpar);
diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c
new file mode 100644
index 0000000..956dbee
--- /dev/null
+++ b/board/freescale/common/fsl_logo_bmp.c
@@ -0,0 +1,878 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*---------------------------------------------------------------------------
+ * FSL_Logo_BMP --
+ *
+ * A 340x128x4bpp BMP logo.
+ *---------------------------------------------------------------------------
+ */
+unsigned int FSL_Logo_BMP[] = {
+0x424d765c,
+0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000,
+0x0000005c,0x0000130b,0x0000130b,0x00001000,0x00000000,0x00000402,0x04000d91,
+0xbc000b51,0x67001536,0x9a000f2a,0x4b005050,0x50009090,0x90000c70,0x92002e2f,
+0x2e00cfcf,0xcf007c82,0x7c00fbfd,0xfb006f70,0x6f00b0b0,0xb00004bd,0xfa000542,
+0xf9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
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+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x008a66d6,0x6a580000,0x00000000,0x00000000,0x000008c6,
+0xd6d6a580,0x00000000,0x00000000,0x000008ca,0x6d6d6a58,0x00000000,0x00000000,
+0x00000004,0x5a6d6da5,0x80000000,0x00000000,0x00008c6d,0x66c50000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x005cad6d,0x6a580000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00033400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000009,
+0x99d9999d,0x50000000,0x00a999d9,0x99960000,0x00000000,0x00000008,0xdbbbbbbb,
+0xbbbb9650,0x00000000,0x00000000,0x008dbbbb,0xbbbbbbb9,0x65000000,0x00000000,
+0x005dbbbb,0xbbbbbbbb,0x96800000,0x00000000,0x00000c9b,0xbbbbbbbb,0xb9640000,
+0x00000000,0x00c9bbbb,0xbbbbbd80,0x00c999d9,0x99980000,0x06999d99,0x99600000,
+0x00000008,0x6bbbbbbb,0xbbbb9d50,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x04ffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xd0000000,0x00cbbbbb,
+0xbbbb0000,0x00000000,0x000004db,0xbbbbbbbb,0xbbbbbbb9,0x50000000,0x00000000,
+0x06bbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,0xbbbbbbbb,0xbbb95000,
+0x00000000,0x00059bbb,0xbbbbbbbb,0xbbbb6800,0x00000000,0x89bbbbbb,0xbbbbbbb9,
+0x806bbbbb,0xbbb40000,0x0abbbbbb,0xbbb00000,0x0000006b,0xbbbbbbbb,0xbbbbbbb9,
+0x50000000,0x00000000,0x00000000,0x00000000,0x00000004,0xffffffff,0x40000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0000000d,0xbbbbbbbb,0x90000000,0x005bbbbb,0xbbbb8000,0x00000000,0x000089bb,
+0xbbbbbbbb,0xbbbbbbbb,0xbd800000,0x00000008,0x9bbbbbbb,0xbbbbbbbb,0xbbbb9800,
+0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00cbbbbb,0xbbbbbbbb,
+0xbbbbbbc0,0x00000000,0xdbbbbbbb,0xbbbbbbbb,0xba6bbbbb,0xbbb80000,0x05bbbbbb,
+0xbbb40000,0x000009bb,0xbbbbbbbb,0xbbbbbbbb,0xb9800000,0x00000000,0x00000000,
+0x00000000,0x000004ff,0xffffffff,0xf3400000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x0000000a,0xbbbbbbbb,0xb0000000,
+0x008bbbbb,0xbbbbc000,0x00000000,0x0000bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,
+0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbc0,0x0000089b,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbb98,0x00000000,0x0abbbbbb,0xbbbbbbbb,0xbbbbbbbd,0x4000000c,0xbbbbbbbb,
+0xbbbbbbbb,0xbb9bbbbb,0xbbb80000,0x08bbbbbb,0xbbb50000,0x00049bbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbc0000,0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
+0xfff30000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000005,0xbbbbbbbb,0xb8000000,0x0009bbbb,0xbbbb6000,0x00000000,
+0x0009bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbb6,0x000089bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x80000000,0x8bbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0x95000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb50000,
+0x00bbbbbb,0xbbb60000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbba000,0x00000000,
+0x00000000,0x00000000,0x043fffff,0xffffffff,0xfffff400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
+0xbc000000,0x000dbbbb,0xbbbb9000,0x00000000,0x005bbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbc00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x60009bbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0x90000000,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb80000b,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbc0000,0x009bbbbb,0xbbbd0000,0x008bbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x003fffff,
+0xffffffff,0xfffffff0,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0xbbbbbbbb,0xb6000000,0x000abbbb,0xbbbbb000,
+0x00000000,0x009bbbbb,0xbbbbbb65,0x5569bbbb,0xbbbbbbc0,0x00000dbb,0xbbbbbbbb,
+0xb6c5569b,0xbbbbbbbb,0xba08bbbb,0xbbbbbbbb,0x96c55c6b,0xbbbbbbbb,0xb6000005,
+0xbbbbbbbb,0xbbbbbddd,0x9bbbbbbb,0xbbb8004b,0xbbbbbbbb,0xb9655cdb,0xbbbbbbbb,
+0xbbbd0000,0x006bbbbb,0xbbbb0000,0x00dbbbbb,0xbbbbbbdc,0x8c69bbbb,0xbbbbbbc0,
+0x00000000,0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffffffff,0x30000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0xdbbbbbbb,0xb9000000,0x0005bbbb,0xbbbbb800,0x00000000,0x00bbbbbb,0xbbbbd000,
+0x0000cbbb,0xbbbbbbb8,0x00000bbb,0xbbbbbbb9,0x0000000c,0xbbbbbbbb,0xbb5006bb,
+0xbbbbbbd8,0x00000000,0x6bbbbbbb,0xbb400006,0xbbbbbbbb,0xbbb50000,0x08dbbbbb,
+0xbbb9000b,0xbbbbbbbb,0x94000008,0xdbbbbbbb,0xbbb90000,0x00cbbbbb,0xbbbb4000,
+0x00bbbbbb,0xbbbbd400,0x0000cbbb,0xbbbbbbb5,0x00000000,0x00000000,0x00000000,
+0x000004ff,0xffffffff,0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x6bbbbbbb,0xbb000000,0x0008bbbb,
+0xbbbbb500,0x00000000,0x0cbbbbbb,0xbbb90000,0x000008bb,0xbbbbbb95,0x00008bbb,
+0xbbbbbb98,0x00000000,0x49bbbbbb,0xbbc0008d,0xbbbbb500,0x00000000,0x0dbbbbbb,
+0xbbc0000b,0xbbbbbbbb,0xbb800000,0x0005bbbb,0xbb98000b,0xbbbbbbbb,0xc0000000,
+0x06bbbbbb,0xbbbb0000,0x008bbbbb,0xbbbb5000,0x08bbbbbb,0xbbb98000,0x0000089b,
+0xbbbbbbbc,0x00000000,0x00000000,0x00000000,0x00000043,0xffffffff,0xffffffff,
+0xfff34000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x5bbbbbbb,0xbb800000,0x0000bbbb,0xbbbbb600,0x00000000,0x0abbbbbb,
+0xbbb50000,0x00000009,0xbbbbbc00,0x0000cbbb,0xbbbbbbc0,0x00000000,0x089bbbbb,
+0xa0000000,0xc9bb8000,0x00000000,0x05bbbbbb,0xbb90000b,0xbbbbbbbb,0xbc000000,
+0x00005bbb,0x95000009,0xbbbbbbbb,0x50000000,0x009bbbbb,0xbbbb5000,0x000bbbbb,
+0xbbbba000,0x0cbbbbbb,0xbbbc0000,0x00000049,0xbbbbba00,0x00000000,0x00000000,
+0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x8bbbbbbb,0xbb500000,
+0x0000dbbb,0xbbbbb900,0x00000000,0x06bbbbbb,0xbbb00000,0x00000004,0xbbbc0000,
+0x0000abbb,0xbbbbbb40,0x00000000,0x0089bba0,0x00000000,0x00680000,0x00000000,
+0x0abbbbbb,0xbbb0008b,0xbbbbbbbb,0xb8000000,0x00000695,0x0000000c,0xbbbbbbbb,
+0xd0000000,0x008bbbbb,0xbbbbc000,0x0009bbbb,0xbbbbd000,0x0cbbbbbb,0xbbb40000,
+0x00000008,0x9bb60000,0x00000000,0x00000000,0x00000000,0x00000000,0x003fffff,
+0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0bbbbbbb,0xbb600000,0x00006bbb,0xbbbbb900,0x00000000,
+0x0dbbbbbb,0xbb900000,0x00000000,0x8c000000,0x00006bbb,0xbbbbbb00,0x00000000,
+0x0008a400,0x00000000,0x00000000,0x00000008,0x6bbbbbbb,0xbbb5005b,0xbbbbbbbb,
+0x90000000,0x00000000,0x00000008,0xbbbbbbbb,0xb8000000,0x000dbbbb,0xbbbb6000,
+0x000dbbbb,0xbbbb9000,0x0abbbbbb,0xbbb00000,0x00000000,0x06000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00003fff,0xffffffff,0xfff40000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0dbbbbbb,
+0xbbd00000,0x00005bbb,0xbbbbbb80,0x00000000,0x06bbbbbb,0xbb900000,0x00000000,
+0x00000000,0x0000abbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0005ad9b,0xbbbbbbbb,0xbbb5008b,0xbbbbbbbb,0x90000000,0x00000000,0x00000000,
+0xdbbbbbbb,0xb9500000,0x000cbbbb,0xbbbb9000,0x000cbbbb,0xbbbbb400,0x0cbbbbbb,
+0xbbb00000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x000004ff,0xffffffff,0xf4000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x06bbbbbb,0xbbb00000,0x00008bbb,0xbbbbbb50,
+0x00000000,0x06bbbbbb,0xbbb00000,0x00000000,0x00000000,0x0000cbbb,0xbbbbbb00,
+0x00000000,0x00000000,0x00000000,0x00000045,0xd9bbbbbb,0xbbbbbbbb,0xbbb5008b,
+0xbbbbbbbb,0x90000000,0x00000000,0x00000000,0x0bbbbbbb,0xbbb95400,0x0004bbbb,
+0xbbbbb000,0x0008bbbb,0xbbbbb800,0x0cbbbbbb,0xbbb00000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,0xfffffff4,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0cbbbbbb,0xbbb80000,0x00000bbb,0xbbbbbb60,0x00000000,0x0cbbbbbb,0xbbbddddd,
+0xdddddddd,0xdddddddd,0xd8005bbb,0xbbbbbbdd,0xdddddddd,0xdddddddd,0xdddd8000,
+0x00008dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbb4000b,0xbbbbbbbb,0x90000000,0x00000000,
+0x00000000,0x05bbbbbb,0xbbbbbb96,0x5000bbbb,0xbbbbb800,0x0000bbbb,0xbbbbba00,
+0x05bbbbbb,0xbbb9dddd,0xdddddddd,0xdddddddd,0xd8000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x43fff400,0x00000000,0x0007e140,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x08bbbbbb,0xbbb50000,0x000009bb,
+0xbbbbbbd0,0x00000000,0x08bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb8004bbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbc000,0x0006bbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbd0000b,0xbbbbbbbb,0xb0000000,0x00000000,0x00000000,0x00cbbbbb,0xbbbbbbbb,
+0xbb9c9bbb,0xbbbbbc00,0x00009bbb,0xbbbbbd00,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00440000,
+0x00000000,0x07eeeee2,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00bbbbbb,0xbbba0000,0x000006bb,0xbbbbbbb0,0x00000000,0x00bbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbc000bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbb6000,0x00dbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb980000d,0xbbbbbbbb,0xb0000000,
+0x00000000,0x00000000,0x00089bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbb600,0x0000dbbb,
+0xbbbbb900,0x00bbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000002,0xeeeeeeee,0x12000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x009bbbbb,0xbbbd0000,
+0x00000cbb,0xbbbbbbb0,0x00000000,0x009bbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xb6000dbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbb6000,0x0cbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0x94000006,0xbbbbbbbb,0xbc000000,0x00000000,0x00000000,0x00000cbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbb900,0x0000cbbb,0xbbbbbb00,0x006bbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xb6000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x000002ee,0xeeeeeeee,0xee140000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x006bbbbb,0xbbb90000,0x000008bb,0xbbbbbbb5,0x00000000,
+0x00abbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb60005bb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbb9000,0x09bbbbbb,0xbbbbbbbb,0xbbbbbb9c,0x00000008,0xbbbbbbbb,
+0xbd000000,0x00000000,0x00000000,0x00000005,0x9bbbbbbb,0xbbbbbbbb,0xbbbbbb00,
+0x00005bbb,0xbbbbbb80,0x00cbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0002eeee,0xeeeeeeee,
+0xeeee7000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00cbbbbb,
+0xbbbb8000,0x000000bb,0xbbbbbbb6,0x00000000,0x008bbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbbbb,0xb60008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbd000,0x0bbbbbbb,
+0xbbbbbbbb,0xbbb96800,0x00000000,0xbbbbbbbb,0xbb000000,0x00000000,0x00000000,
+0x00000000,0x00cd9bbb,0xbbbbbbbb,0xbbbbbb80,0x00000bbb,0xbbbbbbc0,0x000bbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x001eeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x008bbbbb,0xbbbb5000,0x0000009b,0xbbbbbbbb,
+0x00000000,0x0009bbbb,0xbbbb5888,0x88888888,0xcbbbbbbb,0xbd0000db,0xbbbbbbbc,
+0x88888888,0x8885bbbb,0xbbbb9000,0x0bbbbbbb,0xbbbbbb96,0xc8000000,0x00000000,
+0x6bbbbbbb,0xbbc00000,0x00000000,0x00000000,0x00000000,0x0000045c,0x69bbbbbb,
+0xbbbbbbc0,0x000009bb,0xbbbbbb60,0x000dbbbb,0xbbbbc888,0x88888888,0x5bbbbbbb,
+0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0047eeee,
+0xeeeeeeee,0xeeeeeee1,0x40000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x000bbbbb,0xbbbba000,0x000000db,0xbbbbbbbb,0xd0000000,0x000cbbbb,0xbbbb6000,
+0x00000000,0x8bbbbbbb,0xb600005b,0xbbbbbbbd,0x00000000,0x0008bbbb,0xbbbbd000,
+0x0bbbbbbb,0xbbb9c000,0x00000000,0x00000000,0x8bbbbbbb,0xbb900000,0x0000000d,
+0x50000000,0x00000000,0x00000000,0x00008dbb,0xbbbbbb60,0x00000dbb,0xbbbbbb90,
+0x0005bbbb,0xbbbbd000,0x00000000,0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x000041ee,0xeeeeeeee,0xeeeeeeee,0xe2000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x0009bbbb,0xbbbbd000,0x000000cb,
+0xbbbbbbbb,0xb9500000,0x00009bbb,0xbbbbb800,0x00000000,0x5bbbbbbb,0xb6000009,
+0xbbbbbbbb,0x50000000,0x0008bbbb,0xbbbbd000,0x0dbbbbbb,0xbb980000,0x00000000,
+0x00000000,0x06bbbbbb,0xbbbd0000,0x0000004b,0xb9800000,0x00000000,0x00000000,
+0x00000cbb,0xbbbbbbd0,0x00000abb,0xbbbbbbb0,0x00009bbb,0xbbbbb500,0x00000000,
+0x8bbbbbbb,0xbd000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043000,
+0x0000002e,0xeeeeeeee,0xeeeeeeee,0xee120000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x000dbbbb,0xbbbb9000,0x0000008b,0xbbbbbbbb,0xbbb9da58,0x0000cbbb,
+0xbbbbb980,0x00000000,0xdbbbbbbb,0xbc000005,0xbbbbbbbb,0xb0000000,0x0006bbbb,
+0xbbbba000,0x0cbbbbbb,0xbbd00000,0x000000cb,0x50000000,0x08bbbbbb,0xbbbb5000,
+0x0000006b,0xbbb60000,0x0006bbbb,0xbbbb6000,0x000008bb,0xbbbbbbb0,0x000005bb,
+0xbbbbbbb8,0x00005bbb,0xbbbbb980,0x00000000,0x6bbbbbbb,0xba000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x043fff30,0x00000000,0x1eeeeeee,0xeeeeeeee,
+0xeeee1400,0x00000000,0x00000000,0x00000000,0x00000000,0x000cbbbb,0xbbbbb000,
+0x0000000b,0xbbbbbbbb,0xbbbbbbbb,0xb50009bb,0xbbbbbb98,0x00000005,0xbbbbbbbb,
+0xb8000000,0xdbbbbbbb,0xbb800000,0x005bbbbb,0xbbbb5000,0x04bbbbbb,0xbbb00000,
+0x000006bb,0xbd800000,0x00cbbbbb,0xbbbbb600,0x00000cbb,0xbbbbb500,0x0005bbbb,
+0xbbbbb400,0x000000bb,0xbbbbbbb4,0x000004bb,0xbbbbbbbc,0x00000dbb,0xbbbbbb95,
+0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0x3fffffff,0x40000000,0x04eeeeee,0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,
+0x00000000,0x00000008,0x888cbbbb,0xbbbbbc88,0x88800009,0xbbbbbbbb,0xbbbbbbbb,
+0xba0008bb,0xbbbbbbbb,0x680008ab,0xbbbbbbbb,0x90000000,0x89bbbbbb,0xbbb68000,
+0x0cbbbbbb,0xbbbb0000,0x006bbbbb,0xbbb95000,0x0056bbbb,0xbbb60000,0x0009bbbb,
+0xbbbbbbb6,0x588c9bbb,0xbbbbbb90,0x0000bbbb,0xbbbbbd00,0x000005bb,0xbbbbbbb8,
+0x0000009b,0xbbbbbbb6,0x000000bb,0xbbbbbbbb,0x680000cb,0xbbbbbbbb,0xb0000000,
+0x00000000,0x00000000,0x00000000,0x0000043f,0xffffffff,0xf3000000,0x0002eeee,
+0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,0x00000000,0x0000000b,0xbbbbbbbb,
+0xbbbbbbbb,0xbbb5000d,0xbbbbbbbb,0xbbbbbbbb,0xbd0000cb,0xbbbbbbbb,0xbb999bbb,
+0xbbbbbbbb,0x60000000,0x05bbbbbb,0xbbbbbb99,0xbbbbbbbb,0xbbbd0000,0x008bbbbb,
+0xbbbbbb99,0xbbbbbbbb,0xbbbb9c00,0x00009bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,
+0x0000cbbb,0xbbbbbb98,0x000089bb,0xbbbbbbb8,0x0000009b,0xbbbbbbb9,0x0000005b,
+0xbbbbbbbb,0xbbb99bbb,0xbbbbbbbb,0xd0000000,0x00000000,0x00000000,0x00000000,
+0x00003fff,0xffffffff,0xfff30000,0x000001ee,0xeeeeeeee,0xee140000,0x00000000,
+0x00000000,0x00000000,0x00000009,0xbbbbbbbb,0xbbbbbbbb,0xbbbc000a,0xbbbbbbbb,
+0xbbbbbbbb,0xb9000006,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,0x40000000,0x00abbbbb,
+0xbbbbbbbb,0xbbbbbbbb,0xbbb80000,0x0005bbbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbd0,
+0x00008bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x000009bb,0xbbbbbbbb,0x9d99bbbb,
+0xbbbbbbb0,0x0000006b,0xbbbbbbbb,0x00000005,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbbbb,
+0x80000000,0x00000000,0x00000000,0x00000000,0x003fffff,0xffffffff,0xfffff400,
+0x00000041,0xeeeeeeee,0x14000000,0x00000000,0x00000000,0x00000000,0x00000006,
+0xbbbbbbbb,0xbbbbbbbb,0xbbb60008,0xbbbbbbbb,0xbbbbbbbb,0xbb000000,0x6bbbbbbb,
+0xbbbbbbbb,0xbbbbbbbc,0x00000000,0x000abbbb,0xbbbbbbbb,0xbbbbbbbb,0xbb600000,
+0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb50,0x0000049b,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbbbd00,0x000008bb,0xbbbbbbbb,0xbbbbbbbb,0xbbbbbb90,0x0000005b,0xbbbbbbbb,
+0x80000000,0x5bbbbbbb,0xbbbbbbbb,0xbbbbbbb6,0x00005050,0x50500000,0x00000000,
+0x00000000,0x04ffffff,0xffffffff,0xffffff30,0x00000000,0x2eeeee14,0x00000000,
+0x00004400,0x00000000,0x00000000,0x0000000c,0xbbbbbbbb,0xbbbbbbbb,0xbbb90000,
+0xbbbbbbbb,0xbdbbbbbb,0xbb500000,0x05bbbbbb,0xbbbbbbbb,0xbbbbbb90,0x00000000,
+0x00005bbb,0xbbbbbbbb,0xbbbbbbbb,0xb9000000,0x000005bb,0xbbbbbbbb,0xbbbbbbbb,
+0xbbbb9000,0x0000000d,0xbbbbbbbb,0xbbbbbbbb,0xbbbb9000,0x0000005b,0xbbbbbbbb,
+0xbbbbbbbb,0xbbbbbb50,0x0000008b,0xbbbbbbbb,0x50000000,0x05bbbbbb,0xbbbbbbbb,
+0xbbbbbb90,0x0008c068,0x98d00000,0x00000000,0x00000000,0x0004ffff,0xffffffff,
+0xffffffff,0x30000000,0x047e1400,0x00000000,0x0043ff34,0x00000000,0x00000000,
+0x00000008,0xbbbbbbbb,0xbbbbbbbb,0xbbbb0000,0x9bbbbbbb,0xb60a9bbb,0xbbc00000,
+0x008dbbbb,0xbbbbbbbb,0xbbbbbd00,0x00000000,0x000000db,0xbbbbbbbb,0xbbbbbbbb,
+0xd8000000,0x0000008d,0xbbbbbbbb,0xbbbbbbbb,0xbb950000,0x00000000,0x59bbbbbb,
+0xbbbbbbbb,0xbbbd0000,0x00000004,0xdbbbbbbb,0xbbbbbbbb,0xbbbbbc00,0x00000009,
+0xbbbbbbbb,0x60000000,0x000dbbbb,0xbbbbbbbb,0xbbbbbd00,0x0008a06a,0xccd00000,
+0x00000000,0x00000000,0x000003ff,0xffffffff,0xffffffff,0xff400000,0x00040000,
+0x00000000,0x03ffffff,0x30000000,0x00000000,0x00000000,0xdddddbbb,0xbbbbbb9d,
+0xdddd8000,0xdbbbbbbb,0xb90005db,0xbb600000,0x00005dbb,0xbbbbbbbb,0xbbb95000,
+0x00000000,0x00000008,0xdbbbbbbb,0xbbbbbb9c,0x00000000,0x00000000,0x59bbbbbb,
+0xbbbbbbbb,0x95000000,0x00000000,0x00c9bbbb,0xbbbbbbbb,0xb9500000,0x00000000,
+0x059bbbbb,0xbbbbbbbb,0xbbb95000,0x00000009,0xbbbbbbbb,0xd0000000,0x00008dbb,
+0xbbbbbbbb,0xbbb9a000,0x0008a0dd,0x06d00000,0x00000000,0x00000000,0x00000043,
+0xffffffff,0xffffffff,0xfff34000,0x00000000,0x00000043,0xffffffff,0xff400000,
+0x00000000,0x00000000,0x000009bb,0xbbbbbbd0,0x00000000,0x8c5555c5,0x55000000,
+0x85500000,0x0000008c,0xd9bbbbbb,0x9d500000,0x00000000,0x00000000,0x00cd9bbb,
+0xbbb9d500,0x00000000,0x00000000,0x004cd9bb,0xbbbb9dc0,0x00000000,0x00000000,
+0x00005cdb,0xbbbbbb9a,0x50000000,0x00000000,0x0008cdbb,0xbbbbbbb9,0xda800000,
+0x00000006,0xbbbbbbbb,0xb0000000,0x0000000c,0xd9bbbbbb,0x9dc00000,0x0086dc6c,
+0x0cd00000,0x00000000,0x00000000,0x00000000,0x4fffffff,0xffffffff,0xfffff300,
+0x00000000,0x000003ff,0xffffffff,0xffff0000,0x00000000,0x00000000,0x00000dbb,
+0xbbbbbb90,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00008840,
+0x00000000,0x00000000,0x00000000,0x00000008,0x84000000,0x00000000,0x00000000,
+0x00000000,0x88400000,0x00000000,0x00000000,0x00000000,0x08880000,0x00000000,
+0x00000000,0x00000000,0x08888000,0x00000000,0x0000000c,0xbbbbbbbb,0xb8000000,
+0x00000000,0x00008880,0x00000000,0x00888480,0x00800000,0x00000000,0x00000000,
+0x00000000,0x003fffff,0xffffffff,0xfffff400,0x00000000,0x0003ffff,0xffffffff,
+0xfffff300,0x00000000,0x00000000,0x00000abb,0xbbbbbbb8,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000008,0xbbbbbbbb,0xb5000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00043fff,0xffffffff,
+0xfff30000,0x00000000,0x003fffff,0xffffffff,0xfffffff4,0x00000000,0x00000000,
+0x000005bb,0xbbbbbbbb,0x58040000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0xbbbbbbbb,
+0xba000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x000004ff,0xffffffff,0xf3000000,0x00000000,0x00003fff,
+0xffffffff,0xffffffff,0x30000000,0x00000000,0x000000bb,0xbbbbbbbb,0xbbbbb500,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0xdbbbbbbb,0xbd000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000003,
+0xfffffff3,0x00000000,0x00000000,0x000004ff,0xffffffff,0xffffffff,0xff300000,
+0x00000000,0x000000db,0xbbbbbbbb,0xbbbbba00,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x6bbbbbbb,0xb9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x43fff340,0x00000000,0x00021100,
+0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,0x0000008b,0xbbbbbbbb,
+0xbbbbbd00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0xcbbbbbbb,0xbb800000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00430000,0x00000000,0x021eeee2,0x00000000,0x03ffffff,0xffffffff,
+0xfffff300,0x00000000,0x0000000d,0xbbbbbbbb,0xbbbbb900,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x8bbbbbbb,0xbb500000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0x1eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,0x00000000,0x00000000,
+0x9bbbbbbb,0xbbbbbb00,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0bbbbbbb,0xbba00000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000041e,0xeeeeeeee,0xee100000,0x00003fff,
+0xffffffff,0xffff3000,0x00000000,0x00000000,0x0dbbbbbb,0xbbbbbb50,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x09bbbbbb,0xbbd00000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00047eee,0xeeeeeeee,0xeeee2000,0x0000003f,0xffffffff,0xff300000,0x00000000,
+0x00000000,0x0059bbbb,0xbbbbbbc0,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x06bbbbbb,
+0xbb900000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x007eeeee,0xeeeeeeee,0xeeeee140,
+0x00000004,0xffffffff,0x30000000,0x00000000,0x00000000,0x00004c66,0xd66a5800,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00808480,0x84800000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0041eeee,0xeeeeeeee,0xeeeeeee7,0x00000000,0x03ffff34,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00002eee,0xeeeeeeee,
+0xeeeeeeee,0xe2000000,0x004f3400,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0000007e,0xeeeeeeee,0xeeeeeeee,0xee140000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0x1eeeeeee,0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x02eeeeee,0xeeeeeeee,0xeeeeee40,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0007eeee,0xeeeeeeee,0xeeeee400,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000041ee,0xeeeeeeee,
+0xeee20000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0000002e,0xeeeeeeee,0xe2000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x7eeeeee2,0x00000000,0x00000400,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x041ee700,0x00000000,0x0003ff30,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00040000,0x00000000,0x04ffffff,0x40000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000004,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,0xfff30000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x0004ffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x004fffff,0xffffffff,0xfffffff4,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00043fff,0xffffffff,0xffffffff,0x30000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000004ff,0xffffffff,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00047700,0x00000003,0xffffffff,0xffffffff,0xffff4000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x001eeee4,0x00000000,
+0x4fffffff,0xffffffff,0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x7eeeeeee,0x14000000,0x004fffff,0xffffffff,0xffffff30,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x0000007e,0xeeeeeeee,
+0xee200000,0x00003fff,0xffffffff,0xffff3400,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00002eee,0xeeeeeeee,0xeeee4000,0x000004ff,0xffffffff,
+0xfff40000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x002eeeee,
+0xeeeeeeee,0xeeeee140,0x00000004,0xffffffff,0xf4000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0041eeee,0xeeeeeeee,0xeeeeeee7,0x00000000,
+0x43fffff4,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00002eee,0xeeeeeeee,0xeeeeeeee,0x12000000,0x004ff400,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00004000,0x0000007e,0xeeeeeeee,0xeeeeeeee,
+0xee100000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x004fff40,0x00000004,0x1eeeeeee,0xeeeeeeee,0xeeee7000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x4ffffff3,0x00000000,0x02eeeeee,
+0xeeeeeeee,0xeeeeee40,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000043,0xffffffff,0xf3000000,0x0001eeee,0xeeeeeeee,0xeeeee200,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x000043ff,0xffffffff,0xfff40000,
+0x00004eee,0xeeeeeeee,0xeee70000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0043ffff,0xffffffff,0xffff3400,0x0000002e,0xeeeeeeee,0xe7400000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
+0xffffff30,0x00000000,0x1eeeeee7,0x40000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0003ffff,0xffffffff,0xffffffff,0x40000000,0x04eee140,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
+0xffffffff,0xffffffff,0xf3000000,0x00024000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0xffffffff,0xfff30000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x3fffffff,0xffffffff,0xfffff400,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00ffffff,0xffffffff,
+0xfffff300,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x0004ffff,0xffffffff,0xffff3000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x000003ff,
+0xffffffff,0xff400000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x0000004f,0xffffffff,0x30000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x4fffff30,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x003f3000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,
+0x00000000,0x0000babe
+};
diff --git a/board/freescale/common/ft_board.c b/board/freescale/common/ft_board.c
new file mode 100644
index 0000000..6f221af
--- /dev/null
+++ b/board/freescale/common/ft_board.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include "cadmus.h"
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static void cds_pci_fixup(void *blob)
+{
+ int node, tmp[2];
+ const char *path;
+ int len, slot, i;
+ u32 *map = NULL;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ node = fdt_path_offset(blob, path);
+ if (node >= 0) {
+ map = fdt_getprop_w(blob, node, "interrupt-map", &len);
+ }
+ }
+ }
+
+ if (map) {
+ len /= sizeof(u32);
+
+ slot = get_pci_slot();
+
+ for (i=0;i<len;i+=7) {
+ /* We rotate the interrupt pins so that the mapping
+ * changes depending on the slot the carrier card is in.
+ */
+ map[3] = ((map[3] + slot - 2) % 4) + 1;
+ map+=7;
+ }
+ }
+}
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+ cds_pci_fixup(blob);
+#endif
+}
+#endif
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index fd99a93..45dcf4d 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
}
+#ifndef CFG_PIXIS_VBOOT_MASK
+#define CFG_PIXIS_VBOOT_MASK 0x40
+#endif
void set_altbank(void)
{
u8 tmp;
tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
- tmp ^= 0x40;
+ tmp ^= CFG_PIXIS_VBOOT_MASK;
out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
}
diff --git a/board/freescale/common/via.c b/board/freescale/common/via.c
new file mode 100644
index 0000000..4a63d77
--- /dev/null
+++ b/board/freescale/common/via.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+
+/* Config the VIA chip */
+void mpc85xx_config_via(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pci_dev_t bridge;
+ unsigned int cmdstat;
+
+ /* Enable USB and IDE functions */
+ pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
+
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+
+ /*
+ * Force the backplane P2P bridge to have a window
+ * open from 0x00000000-0x00001fff in PCI I/O space.
+ * This allows legacy I/O (i8259, etc) on the VIA
+ * southbridge to be accessed.
+ */
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
+ pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
+ pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
+}
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+ /*
+ * Since the P2P window was forced to cover the fixed
+ * legacy I/O addresses, it is necessary to manually
+ * place the base addresses for the IDE and USB functions
+ * within this window.
+ */
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
+}
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
+}
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
+}
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
+}
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *tab)
+{
+ pciauto_config_device(hose, dev);
+
+ pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
+}
diff --git a/board/freescale/common/via.h b/board/freescale/common/via.h
new file mode 100644
index 0000000..77cfacc
--- /dev/null
+++ b/board/freescale/common/via.h
@@ -0,0 +1,18 @@
+#ifndef _MPC85xx_VIA_H
+void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 1, IDE */
+void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 2, USB ports 0-1 */
+void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 3, USB ports 2-3 */
+void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 5, Power Management */
+void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+
+/* Function 6, AC97 Interface */
+void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab);
+#endif /* _MPC85xx_VIA_H */
diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk
index ce014ed..b42fcc9 100644
--- a/board/freescale/m54455evb/config.mk
+++ b/board/freescale/m54455evb/config.mk
@@ -22,4 +22,6 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/freescale/m54455evb/u-boot.atm b/board/freescale/m54455evb/u-boot.atm
new file mode 100644
index 0000000..bda68e4
--- /dev/null
+++ b/board/freescale/m54455evb/u-boot.atm
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf5445x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/m54455evb/u-boot.int b/board/freescale/m54455evb/u-boot.int
new file mode 100644
index 0000000..e480c29
--- /dev/null
+++ b/board/freescale/m54455evb/u-boot.int
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf5445x/start.o (.text)
+ lib_m68k/traps.o (.text)
+ lib_m68k/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 861c143..42019fb 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -23,9 +23,7 @@
*/
#include <common.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#include <pci.h>
@@ -103,16 +101,6 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index e738613..2fc4fd6 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -184,16 +184,6 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 6ba25d4..6adf7e7 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -27,9 +27,7 @@
#else
#include <asm/mmu.h>
#endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
@@ -169,16 +167,6 @@ int checkboard(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index 6bc35c7..b030422 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -18,10 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
#include <asm/fsl_i2c.h>
@@ -262,37 +261,26 @@ void pci_init_board(void)
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
- int err;
int tmp[2];
+ const char *path;
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
- if (p != NULL) {
- p[0] = hose[0].first_busno;
- p[1] = hose[0].last_busno;
+ path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(hose[0].first_busno);
+ tmp[1] = cpu_to_be32(hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
}
}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 39c0916..3d72eb7 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -32,9 +32,7 @@
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -256,16 +254,6 @@ void sdram_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index ae94a2f..564e436 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -25,10 +25,9 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
@@ -389,58 +388,39 @@ pci_init_board(void)
}
#if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
- int err;
int tmp[2];
+ const char *path;
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
+ path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
#ifdef CONFIG_MPC83XX_PCI2
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
- if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
+ path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
#endif
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[0].first_busno;
- p[1] = pci_hose[0].last_busno;
- }
-
-#ifdef CONFIG_MPC83XX_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[1].first_busno;
- p[1] = pci_hose[1].last_busno;
}
-#endif
}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index c82f784..8c19ad6 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -37,9 +37,7 @@
#else
#include <asm/mmu.h>
#endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -389,16 +387,6 @@ int misc_init_r(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index 5ca094d..d33edf3 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -29,10 +29,9 @@
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -335,58 +334,39 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
- int err;
int tmp[2];
+ const char *path;
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
+ path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
#ifdef CONFIG_MPC83XX_PCI2
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
- if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
- tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
+ path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+ tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
#endif
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[0].first_busno;
- p[1] = pci_hose[0].last_busno;
- }
-
-#ifdef CONFIG_MPC83XX_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len);
- if (p != NULL) {
- p[0] = pci_hose[1].first_busno;
- p[1] = pci_hose[1].last_busno;
}
-#endif
}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index e050cd4..2fcef8b 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -25,9 +25,7 @@
#else
#include <asm/mmu.h>
#endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
@@ -87,6 +85,11 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
+ {5, 0, 1, 0, 2}, /* UART2_SOUT */
+ {5, 1, 2, 0, 3}, /* UART2_CTS */
+ {5, 2, 1, 0, 1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2}, /* UART2_SIN */
+
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
@@ -106,6 +109,9 @@ int board_early_init_f(void)
immr->sysconf.spridr == SPR_8360E_REV21)
bcsr[0xe] = 0x30;
+ /* Enable second UART */
+ bcsr[0x9] &= ~0x01;
+
return 0;
}
@@ -295,19 +301,48 @@ void sdram_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
+ const immap_t *immr = (immap_t *)CFG_IMMR;
+
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+ /*
+ * mpc8360ea pb mds errata 2: RGMII timing
+ * if on mpc8360ea rev. 2.1,
+ * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
+ */
+ if (immr->sysconf.spridr == SPR_8360_REV21 ||
+ immr->sysconf.spridr == SPR_8360E_REV21) {
+ int nodeoffset;
+ const char *prop;
+ const char *path;
+
+ nodeoffset = fdt_path_offset(fdt, "/aliases");
+ if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+ /* fixup UCC 1 if using rgmii-id mode */
+ path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+ if (path) {
+ prop = fdt_getprop(blob, nodeoffset,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_setprop(blob, nodeoffset, "phy-connection-type",
+ "rgmii-rxid", sizeof("rgmii-rxid"));
+ }
+#endif
+#if defined(CONFIG_HAS_ETH1)
+ /* fixup UCC 2 if using rgmii-id mode */
+ path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+ if (path) {
+ prop = fdt_getprop(blob, nodeoffset,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_setprop(blob, nodeoffset, "phy-connection-type",
+ "rgmii-rxid", sizeof("rgmii-rxid"));
+ }
+#endif
+ }
+ }
}
#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index cf7ef90..4a0d460 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -18,10 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
#include <asm/fsl_i2c.h>
@@ -262,37 +261,26 @@ void pci_init_board(void)
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
- int err;
int tmp[2];
+ const char *path;
- nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
- if (p != NULL) {
- p[0] = hose[0].first_busno;
- p[1] = hose[0].last_busno;
+ path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(hose[0].first_busno);
+ tmp[1] = cpu_to_be32(hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
}
}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile
new file mode 100644
index 0000000..5ec7a87
--- /dev/null
+++ b/board/freescale/mpc837xemds/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o pci.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc837xemds/config.mk b/board/freescale/mpc837xemds/config.mk
new file mode 100644
index 0000000..63c5fc3
--- /dev/null
+++ b/board/freescale/mpc837xemds/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MPC837xEMDS
+#
+
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
new file mode 100644
index 0000000..6925d23
--- /dev/null
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * CREDITS: Kim Phillips contribute to LIBFDT code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spd.h>
+#if defined(CONFIG_SPD_EEPROM)
+#include <spd_sdram.h>
+#endif
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
+#endif
+
+int board_early_init_f(void)
+{
+ u8 *bcsr = (u8 *)CFG_BCSR;
+
+ /* Enable flash write */
+ bcsr[0x9] &= ~0x04;
+ /* Clear all of the interrupt of BCSR */
+ bcsr[0xe] = 0xff;
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+ pib_init();
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+int fixed_sdram(void);
+
+long int initdram(int board_type)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = 0;
+
+ if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ return -1;
+
+#if defined(CONFIG_SPD_EEPROM)
+ msize = spd_sdram();
+#else
+ msize = fixed_sdram();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+ /* Initialize DDR ECC byte */
+ ddr_enable_ecc(msize * 1024 * 1024);
+#endif
+
+ /* return total bus DDR size(bytes) */
+ return (msize * 1024 * 1024);
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *) CFG_IMMR;
+ u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+
+ im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
+ im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
+
+#if (CFG_DDR_SIZE != 512)
+#warning Currenly any ddr size other than 512 is not supported
+#endif
+ im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+ udelay(50000);
+
+ im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+ udelay(1000);
+
+ im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
+ im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+ udelay(1000);
+
+ im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+ im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
+ im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+ im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
+ im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+ im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
+ im->ddr.sdram_mode = CFG_DDR_MODE;
+ im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+ im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+ __asm__ __volatile__("sync");
+ udelay(1000);
+
+ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ udelay(2000);
+ return CFG_DDR_SIZE;
+}
+#endif /*!CFG_SPD_EEPROM */
+
+int checkboard(void)
+{
+ puts("Board: Freescale MPC837xEMDS\n");
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+ ft_pci_setup(blob, bd);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
new file mode 100644
index 0000000..ab90979
--- /dev/null
+++ b/board/freescale/mpc837xemds/pci.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <asm/mmu.h>
+#include <asm/io.h>
+#include <common.h>
+#include <mpc83xx.h>
+#include <pci.h>
+#include <i2c.h>
+#include <asm/fsl_i2c.h>
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+ {
+ bus_start: CFG_PCI_MEM_BASE,
+ phys_start: CFG_PCI_MEM_PHYS,
+ size: CFG_PCI_MEM_SIZE,
+ flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+ },
+ {
+ bus_start: CFG_PCI_MMIO_BASE,
+ phys_start: CFG_PCI_MMIO_PHYS,
+ size: CFG_PCI_MMIO_SIZE,
+ flags: PCI_REGION_MEM
+ },
+ {
+ bus_start: CFG_PCI_IO_BASE,
+ phys_start: CFG_PCI_IO_PHYS,
+ size: CFG_PCI_IO_SIZE,
+ flags: PCI_REGION_IO
+ }
+};
+
+void pci_init_board(void)
+{
+ volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+ volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+ volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+ struct pci_region *reg[] = { pci_regions };
+
+ /* Enable all 5 PCI_CLK_OUTPUTS */
+ clk->occr |= 0xf8000000;
+ udelay(2000);
+
+ /* Configure PCI Local Access Windows */
+ pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+ pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
+
+ pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+ pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
+
+ udelay(2000);
+
+ mpc83xx_pci_init(1, reg, 0);
+}
+#endif /* CONFIG_PCI */
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
new file mode 100644
index 0000000..2913650
--- /dev/null
+++ b/board/freescale/mpc8540ads/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8540ads/config.mk b/board/freescale/mpc8540ads/config.mk
new file mode 100644
index 0000000..92f8931
--- /dev/null
+++ b/board/freescale/mpc8540ads/config.mk
@@ -0,0 +1,33 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S
new file mode 100644
index 0000000..544fde9
--- /dev/null
+++ b/board/freescale/mpc8540ads/init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 8, 9: 128M DDR
+ * 0x00000000 64M DDR System memory
+ * 0x04000000 64M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+#error("Update the number of table entries in tlb1_entry")
+ .long TLB1_MAS0(1, 8, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1, 9, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x05
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4
+ entry_end
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
new file mode 100644
index 0000000..35f5eea
--- /dev/null
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,348 @@
+ /*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf(" PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint temp_ddrdll = 0;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /*
+ * Initialize SDRAM.
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts(" SDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+
+static struct pci_controller hose;
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
new file mode 100644
index 0000000..a7c68b3
--- /dev/null
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8540ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8540ads/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8541cds/Makefile b/board/freescale/mpc8541cds/Makefile
new file mode 100644
index 0000000..7f53098
--- /dev/null
+++ b/board/freescale/mpc8541cds/Makefile
@@ -0,0 +1,60 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8541cds/config.mk b/board/freescale/mpc8541cds/config.mk
new file mode 100644
index 0000000..17cc8bc
--- /dev/null
+++ b/board/freescale/mpc8541cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8541cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1
diff --git a/board/freescale/mpc8541cds/init.S b/board/freescale/mpc8541cds/init.S
new file mode 100644
index 0000000..978bda5
--- /dev/null
+++ b/board/freescale/mpc8541cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 6
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+ entry_end
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
new file mode 100644
index 0000000..9ab98d4
--- /dev/null
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -0,0 +1,534 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf (" PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ (pci1_speed == 33000000) ? "33" :
+ (pci1_speed == 66000000) ? "66" : "unknown",
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~0x8000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller hose[] = {
+ { config_table: pci_mpc85xxcds_config_table,},
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
new file mode 100644
index 0000000..4360d67
--- /dev/null
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8541cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8541cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 68ccba7..084d4b8 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -27,13 +27,6 @@
#include <config.h>
#include <mpc85xx.h>
-#define LAWAR_TRGT_PCI1 0x00000000
-#define LAWAR_TRGT_PCIE1 0x00200000
-#define LAWAR_TRGT_PCIE2 0x00100000
-#define LAWAR_TRGT_PCIE3 0x00300000
-#define LAWAR_TRGT_LBC 0x00400000
-#define LAWAR_TRGT_DDR 0x00f00000
-
/*
* TLB0 and TLB1 Entries
*
@@ -212,31 +205,31 @@ law_entry:
.long (4f-3f)/8
3:
.long 0
- .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
/* contains both PCIE3 MEM & IO space */
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
- .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
4:
entry_end
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 76d9091..66cb536 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -29,14 +29,11 @@
#include <asm/io.h>
#include <spd.h>
#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/pixis.h"
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
@@ -52,10 +49,9 @@ int board_early_init_f (void)
int checkboard (void)
{
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
- volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
@@ -149,8 +145,7 @@ int first_free_busno=0;
void
pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
uint devdisr = gur->devdisr;
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -227,7 +222,7 @@ pci_init_board(void)
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32(CFG_PCIE3_MEM_BASE);
+ in_be32((u32 *)CFG_PCIE3_MEM_BASE);
} else {
printf (" PCIE3: disabled\n");
}
@@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
return val;
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ int node, tmp[2];
+ const char *path;
ft_cpu_setup(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
-#endif
-#ifdef CONFIG_PCIE1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci2", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCIE3
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
- debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci3", NULL);
+ if (path) {
+ tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
+ }
}
#endif
diff --git a/board/freescale/mpc8548cds/Makefile b/board/freescale/mpc8548cds/Makefile
new file mode 100644
index 0000000..7f53098
--- /dev/null
+++ b/board/freescale/mpc8548cds/Makefile
@@ -0,0 +1,60 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8548cds/config.mk b/board/freescale/mpc8548cds/config.mk
new file mode 100644
index 0000000..b23bc87
--- /dev/null
+++ b/board/freescale/mpc8548cds/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8548cds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
new file mode 100644
index 0000000..a83a095
--- /dev/null
+++ b/board/freescale/mpc8548cds/init.S
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+
+#ifdef CFG_RIO_MEM_PHYS
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+
+#ifdef CFG_PCI1_MEM_PHYS
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCI2_MEM_PHYS
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+#ifdef CFG_PCIE1_MEM_PHYS
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
+
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+#ifdef CFG_RIO_MEM_PHYS
+ .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
+4:
+ entry_end
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
new file mode 100644
index 0000000..47e2dd8
--- /dev/null
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -0,0 +1,547 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ /*
+ * Fix CPU2 errata: A core hang possible while executing a
+ * msync instruction and a snoopable transaction from an I/O
+ * master tagged to make quick forward progress is present.
+ */
+ ecm->eebpcr |= (1 << 16);
+
+ /*
+ * Hack TSEC 3 and 4 IO voltages.
+ */
+ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8548 uses "new" 15-16 style addressing.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it.
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+static struct pci_controller pci1_hose = {
+ config_table: pci_mpc85xxcds_config_table};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_config_table *table;
+
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+
+ /* relocate config table pointers */
+ hose->config_table = \
+ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+ for (table = hose->config_table; table && table->vendor; table++)
+ table->config_device += gd->reloc_off;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+}
+
+int last_stage_init(void)
+{
+ unsigned short temp;
+
+ /* Change the resistors for the PHY */
+ /* This is needed to get the RGMII working for the 1.3+
+ * CDS cards */
+ if (get_board_version() == 0x13) {
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 18);
+
+ miiphy_read(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, &temp);
+
+ temp = (temp & 0xf03f);
+ temp |= 2 << 9; /* 36 ohm */
+ temp |= 2 << 6; /* 39 ohm */
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, temp);
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 29, 3);
+
+ miiphy_write(CONFIG_TSEC1_NAME,
+ TSEC1_PHY_ADDR, 30, 0x8000);
+ }
+
+ return 0;
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
new file mode 100644
index 0000000..ee772d3
--- /dev/null
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8548cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8548cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8555cds/Makefile b/board/freescale/mpc8555cds/Makefile
new file mode 100644
index 0000000..7f53098
--- /dev/null
+++ b/board/freescale/mpc8555cds/Makefile
@@ -0,0 +1,60 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/cadmus.o \
+ ../common/eeprom.o \
+ ../common/ft_board.o \
+ ../common/via.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8555cds/config.mk b/board/freescale/mpc8555cds/config.mk
new file mode 100644
index 0000000..5dcaa77
--- /dev/null
+++ b/board/freescale/mpc8555cds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2004 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8555cds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1
diff --git a/board/freescale/mpc8555cds/init.S b/board/freescale/mpc8555cds/init.S
new file mode 100644
index 0000000..978bda5
--- /dev/null
+++ b/board/freescale/mpc8555cds/init.S
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xa0000000 256M PCI2 MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xb0000000 256M PCI2 MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ * 0xe300_0000 16M PCI2 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 1M Non-cacheable, guarded
+ * 0xf8000000 1M CADMUS registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M
+ * 0xe210_0000 0xe21f_ffff PCI2 IO 1M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long 6
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5
+ entry_end
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
new file mode 100644
index 0000000..74c220d
--- /dev/null
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -0,0 +1,534 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "../common/cadmus.h"
+#include "../common/eeprom.h"
+#include "../common/via.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ /* PCI slot in USER bits CSR[6:7] by convention. */
+ uint pci_slot = get_pci_slot ();
+
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
+ uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+
+ uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ uint cpu_board_rev = get_cpu_board_revision ();
+
+ printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
+ get_board_version (), pci_slot);
+
+ printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
+ MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
+
+ printf (" PCI1: %d bit, %s MHz, %s\n",
+ (pci1_32) ? 32 : 64,
+ (pci1_speed == 33000000) ? "33" :
+ (pci1_speed == 66000000) ? "66" : "unknown",
+ pci1_clk_sel ? "sync" : "async");
+
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+ uint temp_lbcdll;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr |= 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr &= (~0x80000000); /* DLL Enabled */
+
+ } else {
+ lbc->lcrr &= (~0x8000000); /* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint cpu_board_rev;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * Determine which address lines to use baed on CPU board rev.
+ */
+ cpu_board_rev = get_cpu_board_revision();
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+ } else {
+ /*
+ * Assume something unable to identify itself is
+ * really old, and likely has lines 16/17 mapped.
+ */
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+ }
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PCI
+/* For some reason the Tundra PCI bridge shows up on itself as a
+ * different device. Work around that by refusing to configure it
+ */
+void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
+
+static struct pci_config_table pci_mpc85xxcds_config_table[] = {
+ {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
+ mpc85xx_config_via_usbide, {0,0,0}},
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
+ mpc85xx_config_via_power, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
+ {},
+};
+
+
+static struct pci_controller hose[] = {
+ {
+ config_table: pci_mpc85xxcds_config_table,
+ },
+#ifdef CONFIG_MPC85XX_PCI2
+ {},
+#endif
+};
+
+#endif
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(hose);
+#endif
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose[0].last_busno - hose[0].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = hose[1].last_busno - hose[1].first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
new file mode 100644
index 0000000..df21ea8
--- /dev/null
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8555cds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8555cds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ drivers/net/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
new file mode 100644
index 0000000..2913650
--- /dev/null
+++ b/board/freescale/mpc8560ads/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+SOBJS := init.o
+#SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8560ads/config.mk b/board/freescale/mpc8560ads/config.mk
new file mode 100644
index 0000000..9aef2bb
--- /dev/null
+++ b/board/freescale/mpc8560ads/config.mk
@@ -0,0 +1,32 @@
+# Copyright 2004 Freescale Semiconductor.
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
diff --git a/board/freescale/mpc8560ads/init.S b/board/freescale/mpc8560ads/init.S
new file mode 100644
index 0000000..544fde9
--- /dev/null
+++ b/board/freescale/mpc8560ads/init.S
@@ -0,0 +1,280 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long 13
+
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ * 0xc0000000 256M Rapid IO MEM First half
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0xd0000000 256M Rapid IO MEM Second half
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 5: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 16M PCI1 IO
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 6: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 7: 16K Non-cacheable, guarded
+ * 0xf8000000 16K BCSR registers
+ */
+ .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+ /*
+ * TLB 8, 9: 128M DDR
+ * 0x00000000 64M DDR System memory
+ * 0x04000000 64M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+#error("Update the number of table entries in tlb1_entry")
+ .long TLB1_MAS0(1, 8, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1, 9, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
+
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M
+ * 0xe000_0000 0xe000_ffff CCSR 1M
+ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
+ * 0xf000_0000 0xf7ff_ffff SDRAM 128M
+ * 0xf800_0000 0xf80f_ffff BCSR 1M
+ * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x05
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4
+ entry_end
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
new file mode 100644
index 0000000..bb7f11b
--- /dev/null
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+} bcsr_t;
+
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+ volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+ /* reset Giga bit Ethernet port if needed here */
+
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ /* reset PHY */
+ miiphy_reset("FCC1 ETHERNET", 0x0);
+
+ /* change PHY address to 0x02 */
+ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+ bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+ PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+
+int checkboard (void)
+{
+ puts("Board: ADS\n");
+
+#ifdef CONFIG_PCI
+ printf(" PCI1: 32 bit, %d MHz (compiled)\n",
+ CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+ printf(" PCI1: disabled\n");
+#endif
+
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init();
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint temp_ddrdll = 0;
+
+ /*
+ * Work around to stabilize DDR DLL
+ */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ /*
+ * Initialize SDRAM.
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ /*
+ * Errata LBC11.
+ * Fix Local Bus clock glitch when DLL is enabled.
+ *
+ * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+ * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * Between 66 and 133, the DLL is enabled with an override workaround.
+ */
+
+ get_sys_info(&sysinfo);
+ clkdiv = lbc->lcrr & 0x0f;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ if (lbc_hz < 66) {
+ lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
+
+ } else if (lbc_hz >= 133) {
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+ } else {
+ /*
+ * On REV1 boards, need to change CLKDIV before enable DLL.
+ * Default CLKDIV is 8, change it to 4 temporarily.
+ */
+ uint pvr = get_pvr();
+ uint temp_lbcdll = 0;
+
+ if (pvr == PVR_85xx_REV1) {
+ /* FIXME: Justify the high bit here. */
+ lbc->lcrr = 0x10000004;
+ }
+
+ lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+ udelay(200);
+
+ /*
+ * Sample LBC DLL ctrl reg, upshift it to set the
+ * override bits.
+ */
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
+ asm("sync;isync;msync");
+ }
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+ puts(" SDRAM: ");
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+
+ /*
+ * Configure the SDRAM controller.
+ */
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ } },
+ { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif /* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+ pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = hose.last_busno - hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
new file mode 100644
index 0000000..c2cba61
--- /dev/null
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8560ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8560ads/init.o (.text)
+ cpu/mpc85xx/commproc.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/serial_scc.o (.text)
+ cpu/mpc85xx/ether_fcc.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/spd_sdram.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8568mds/Makefile b/board/freescale/mpc8568mds/Makefile
new file mode 100644
index 0000000..643fbc0
--- /dev/null
+++ b/board/freescale/mpc8568mds/Makefile
@@ -0,0 +1,56 @@
+#
+# Copyright 2004-2007 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o bcsr.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
new file mode 100644
index 0000000..aae0f98
--- /dev/null
+++ b/board/freescale/mpc8568mds/bcsr.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include "bcsr.h"
+
+void enable_8568mds_duart()
+{
+ volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060);
+ volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070);
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
+ *devices = 0; /* Enable all peripheral devices */
+ bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
+}
+
+void enable_8568mds_flash_write()
+{
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[9] |= 0x01;
+}
+
+void disable_8568mds_flash_write()
+{
+ volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[9] &= ~(0x01);
+}
+
+void enable_8568mds_qe_mdio()
+{
+ u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[7] |= 0x01;
+}
diff --git a/board/freescale/mpc8568mds/bcsr.h b/board/freescale/mpc8568mds/bcsr.h
new file mode 100644
index 0000000..aefd9bf
--- /dev/null
+++ b/board/freescale/mpc8568mds/bcsr.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions
+ * BCSR 0 *
+ 0:3 ccb sys pll
+ 4:6 cfg core pll
+ 7 cfg boot seq
+
+ * BCSR 1 *
+ 0:2 cfg rom lock
+ 3:5 cfg host agent
+ 6 PCI IO
+ 7 cfg RIO size
+
+ * BCSR 2 *
+ 0:4 QE PLL
+ 5 QE clock
+ 6 cfg PCI arbiter
+
+ * BCSR 3 *
+ 0 TSEC1 reduce
+ 1 TSEC2 reduce
+ 2:3 TSEC1 protocol
+ 4:5 TSEC2 protocol
+ 6 PHY1 slave
+ 7 PHY2 slave
+
+ * BCSR 4 *
+ 4 clock enable
+ 5 boot EPROM
+ 6 GETH transactive reset
+ 7 BRD write potect
+
+ * BCSR 5 *
+ 1:3 Leds 1-3
+ 4 UPC1 enable
+ 5 UPC2 enable
+ 6 UPC2 pos
+ 7 RS232 enable
+
+ * BCSR 6 *
+ 0 CFG ver 0
+ 1 CFG ver 1
+ 6 Register config led
+ 7 Power on reset
+
+ * BCSR 7 *
+ 2 board host mode indication
+ 5 enable TSEC1 PHY
+ 6 enable TSEC2 PHY
+
+ * BCSR 8 *
+ 0 UCC GETH1 enable
+ 1 UCC GMII enable
+ 3 UCC TBI enable
+ 5 UCC MII enable
+ 7 Real time clock reset
+
+ * BCSR 9 *
+ 0 UCC2 GETH enable
+ 1 UCC2 GMII enable
+ 3 UCC2 TBI enable
+ 5 UCC2 MII enable
+ 6 Ready only - indicate flash ready after burning
+ 7 Flash write protect
+*/
+
+/*BCSR Utils functions*/
+
+void enable_8568mds_duart(void);
+void enable_8568mds_flash_write(void);
+void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
+
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8568mds/config.mk b/board/freescale/mpc8568mds/config.mk
new file mode 100644
index 0000000..021522c
--- /dev/null
+++ b/board/freescale/mpc8568mds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8568mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8568=1
diff --git a/board/freescale/mpc8568mds/init.S b/board/freescale/mpc8568mds/init.S
new file mode 100644
index 0000000..e36036d
--- /dev/null
+++ b/board/freescale/mpc8568mds/init.S
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ * Copyright 2002,2003, Motorola Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif
+
+ /*
+ * TLB0 16K Cacheable, non-guarded
+ * 0xd001_0000 16K Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH (upper half)
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x1000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x1000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 1: 16M Non-cacheable, guarded
+ * 0xfe000000 16M FLASH (lower half)
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 2: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 3: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe200_0000 8M PCI1 IO
+ * 0xe280_0000 8M PCIe IO
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 4: 64M Cacheable, non-guarded
+ * 0xf000_0000 64M LBC SDRAM
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLBe 5: 256K Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
+ *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
+ *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * The defines below are 1-off of the actual LAWAR0 usage.
+ * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ */
+
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+
+#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+
+#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+
+/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
+#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+ .section .bootpg, "ax"
+ .globl law_entry
+
+law_entry:
+ entry_start
+ .long (4f-3f)/8
+3:
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+ .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6
+4:
+ entry_end
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
new file mode 100644
index 0000000..460cb1b
--- /dev/null
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {4, 10, 1, 0, 2}, /* TxD0 */
+ {4, 9, 1, 0, 2}, /* TxD1 */
+ {4, 8, 1, 0, 2}, /* TxD2 */
+ {4, 7, 1, 0, 2}, /* TxD3 */
+ {4, 23, 1, 0, 2}, /* TxD4 */
+ {4, 22, 1, 0, 2}, /* TxD5 */
+ {4, 21, 1, 0, 2}, /* TxD6 */
+ {4, 20, 1, 0, 2}, /* TxD7 */
+ {4, 15, 2, 0, 2}, /* RxD0 */
+ {4, 14, 2, 0, 2}, /* RxD1 */
+ {4, 13, 2, 0, 2}, /* RxD2 */
+ {4, 12, 2, 0, 2}, /* RxD3 */
+ {4, 29, 2, 0, 2}, /* RxD4 */
+ {4, 28, 2, 0, 2}, /* RxD5 */
+ {4, 27, 2, 0, 2}, /* RxD6 */
+ {4, 26, 2, 0, 2}, /* RxD7 */
+ {4, 11, 1, 0, 2}, /* TX_EN */
+ {4, 24, 1, 0, 2}, /* TX_ER */
+ {4, 16, 2, 0, 2}, /* RX_DV */
+ {4, 30, 2, 0, 2}, /* RX_ER */
+ {4, 17, 2, 0, 2}, /* RX_CLK */
+ {4, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+
+ /* GETH2 */
+ {5, 10, 1, 0, 2}, /* TxD0 */
+ {5, 9, 1, 0, 2}, /* TxD1 */
+ {5, 8, 1, 0, 2}, /* TxD2 */
+ {5, 7, 1, 0, 2}, /* TxD3 */
+ {5, 23, 1, 0, 2}, /* TxD4 */
+ {5, 22, 1, 0, 2}, /* TxD5 */
+ {5, 21, 1, 0, 2}, /* TxD6 */
+ {5, 20, 1, 0, 2}, /* TxD7 */
+ {5, 15, 2, 0, 2}, /* RxD0 */
+ {5, 14, 2, 0, 2}, /* RxD1 */
+ {5, 13, 2, 0, 2}, /* RxD2 */
+ {5, 12, 2, 0, 2}, /* RxD3 */
+ {5, 29, 2, 0, 2}, /* RxD4 */
+ {5, 28, 2, 0, 2}, /* RxD5 */
+ {5, 27, 2, 0, 3}, /* RxD6 */
+ {5, 26, 2, 0, 2}, /* RxD7 */
+ {5, 11, 1, 0, 2}, /* TX_EN */
+ {5, 24, 1, 0, 2}, /* TX_ER */
+ {5, 16, 2, 0, 2}, /* RX_DV */
+ {5, 30, 2, 0, 2}, /* RX_ER */
+ {5, 17, 2, 0, 2}, /* RX_CLK */
+ {5, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 6, 3, 0, 2}, /* MDIO */
+ {4, 5, 1, 0, 2}, /* MDC */
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8568mds_duart();
+ enable_8568mds_flash_write();
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+ enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CFG_I2C2_OFFSET
+ /* Enable I2C2_SCL and I2C2_SDA */
+ volatile struct par_io *port_c;
+ port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+ port_c->cpdir2 |= 0x0f000000;
+ port_c->cppar2 &= ~0x0f000000;
+ port_c->cppar2 |= 0x0a000000;
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8568 MDS\n");
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ {
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+
+ gur->ddrdllcr = 0x81000000;
+ asm("sync;isync;msync");
+ udelay(200);
+ }
+#endif
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ /*
+ * SDRAM Initialization
+ */
+ sdram_init();
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & 0x0f) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ gur->lbiuiplldcr1 = 0x00078080;
+ if (clkdiv == 16) {
+ gur->lbiuiplldcr0 = 0x7c0f1bf0;
+ } else if (clkdiv == 8) {
+ gur->lbiuiplldcr0 = 0x6c0f1bf0;
+ } else if (clkdiv == 4) {
+ gur->lbiuiplldcr0 = 0x5c0f1bf0;
+ }
+
+ lbc->lcrr |= 0x00030000;
+
+ asm("sync;isync;msync");
+}
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+void
+sdram_init(void)
+{
+#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+
+ uint idx;
+ volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+ uint lsdmr_common;
+
+ puts(" SDRAM: ");
+
+ print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+ /*
+ * Setup SDRAM Base and Option Registers
+ */
+ lbc->or2 = CFG_OR2_PRELIM;
+ asm("msync");
+
+ lbc->br2 = CFG_BR2_PRELIM;
+ asm("msync");
+
+ lbc->lbcr = CFG_LBC_LBCR;
+ asm("msync");
+
+
+ lbc->lsrt = CFG_LBC_LSRT;
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("msync");
+
+ /*
+ * MPC8568 uses "new" 15-16 style addressing.
+ */
+ lsdmr_common = CFG_LBC_LSDMR_COMMON;
+ lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+
+ /*
+ * Issue PRECHARGE ALL command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue 8 AUTO REFRESH commands.
+ */
+ for (idx = 0; idx < 8; idx++) {
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+ }
+
+ /*
+ * Issue 8 MODE-set command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(100);
+
+ /*
+ * Issue NORMAL OP command.
+ */
+ lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+ asm("sync;msync");
+ *sdram_addr = 0xff;
+ ppcDcbf((unsigned long) sdram_addr);
+ udelay(200); /* Overkill. Must wait > 200 bus cycles */
+
+#endif /* enable SDRAM init */
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_PCI)
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc8568mds_config_table[] = {
+ {
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ pci_cfgfunc_config_device,
+ {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
+ },
+ {}
+};
+#endif
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc8568mds_config_table,
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno = 0;
+
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC2/3 to PCI bus
+ */
+
+ /*switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0x00;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf9;
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ asm("eieio");
+}
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCI1
+{
+ pib_init();
+
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_32 = 1; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = 66666000;
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno = hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+ }
+}
+#endif
diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
new file mode 100644
index 0000000..4682041
--- /dev/null
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+SECTIONS
+{
+ /* ELIOR - From RAM: From FLASH: 0xFFFFFFFC*/
+ .resetvec 0xFFFFFFFC:
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /*(ELIOR - From RAM: From FLASH: 0xFFFFF000*/
+ .bootpg 0xFFFFF000:
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8568mds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8568mds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
new file mode 100644
index 0000000..76087c1
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -0,0 +1,59 @@
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/sys_eeprom.o \
+ ../common/pixis.o \
+ mpc8610hpcd_diu.o \
+ ../common/fsl_diu_fb.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk
new file mode 100644
index 0000000..64ac4dc
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/config.mk
@@ -0,0 +1,25 @@
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2
diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S
new file mode 100644
index 0000000..4d811e1
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/init.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <config.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mpc86xx.h>
+
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCIE1 0x00200000
+#define LAWAR_TRGT_PCIE2 0x00100000
+#define LAWAR_TRGT_LBC 0x00400000
+#define LAWAR_TRGT_DDR 0x00f00000
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#else
+#define LAWBAR1 0
+#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ addi r4,r7,0
+ addi r5,r7,0
+
+ /* Skip LAWAR0, start at LAWAR1 */
+ lis r6,LAWBAR1@h
+ ori r6,r6,LAWBAR1@l
+ stwu r6, 0xc28(r4)
+
+ lis r6,LAWAR1@h
+ ori r6,r6,LAWAR1@l
+ stwu r6, 0xc30(r5)
+
+ /* LAWBAR2, LAWAR2 */
+ lis r6,LAWBAR2@h
+ ori r6,r6,LAWBAR2@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR2@h
+ ori r6,r6,LAWAR2@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR3, LAWAR3 */
+ lis r6,LAWBAR3@h
+ ori r6,r6,LAWBAR3@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR3@h
+ ori r6,r6,LAWAR3@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR4, LAWAR4 */
+ lis r6,LAWBAR4@h
+ ori r6,r6,LAWBAR4@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR4@h
+ ori r6,r6,LAWAR4@l
+ stwu r6, 0x20(r5)
+ /* LAWBAR5, LAWAR5 */
+ lis r6,LAWBAR5@h
+ ori r6,r6,LAWBAR5@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR5@h
+ ori r6,r6,LAWAR5@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR6, LAWAR6 */
+ lis r6,LAWBAR6@h
+ ori r6,r6,LAWBAR6@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR6@h
+ ori r6,r6,LAWAR6@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR7, LAWAR7 */
+ lis r6,LAWBAR7@h
+ ori r6,r6,LAWBAR7@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR7@h
+ ori r6,r6,LAWAR7@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR8, LAWAR8 */
+ lis r6,LAWBAR8@h
+ ori r6,r6,LAWBAR8@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR8@h
+ ori r6,r6,LAWAR8@l
+ stwu r6, 0x20(r5)
+
+ /* LAWBAR9, LAWAR9 */
+ lis r6,LAWBAR9@h
+ ori r6,r6,LAWBAR9@l
+ stwu r6, 0x20(r4)
+
+ lis r6,LAWAR9@h
+ ori r6,r6,LAWAR9@l
+ stwu r6, 0x20(r5)
+
+ blr
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
new file mode 100644
index 0000000..617881a
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define DEBUG
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <asm/io.h>
+
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+/* called before any console output */
+int board_early_init_f(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+
+ gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ u8 tmp_val, version;
+
+ /*Do not use 8259PIC*/
+ tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
+
+ /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
+ version = in8(PIXIS_BASE + PIXIS_PVER);
+ if(version >= 0x07) {
+ tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
+ }
+
+ /* Using this for DIU init before the driver in linux takes over
+ * Enable the TFP410 Encoder (I2C address 0x38)
+ */
+
+ tmp_val = 0xBF;
+ i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+ tmp_val = 0x10;
+ i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+ mpc8610hpcd_diu_init();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+ puts("Board: MPC8610HPCD\n");
+
+ mcm->abcr |= 0x00010000; /* 0 */
+ mcm->hpmr3 = 0x80000008; /* 4c */
+ mcm->hpmr0 = 0;
+ mcm->hpmr1 = 0;
+ mcm->hpmr2 = 0;
+ mcm->hpmr4 = 0;
+ mcm->hpmr5 = 0;
+
+ return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+ puts(" DDR: ");
+ return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ puts("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ puts("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+long int fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ uint d_init;
+
+ ddr->cs0_bnds = 0x0000001f;
+ ddr->cs0_config = 0x80010202;
+
+ ddr->ext_refrec = 0x00000000;
+ ddr->timing_cfg_0 = 0x00260802;
+ ddr->timing_cfg_1 = 0x3935d322;
+ ddr->timing_cfg_2 = 0x14904cc8;
+ ddr->sdram_mode_1 = 0x00480432;
+ ddr->sdram_mode_2 = 0x00000000;
+ ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
+ ddr->sdram_data_init = 0xDEADBEEF;
+ ddr->sdram_clk_cntl = 0x03800000;
+ ddr->sdram_cfg_2 = 0x04400010;
+
+#if defined(CONFIG_DDR_ECC)
+ ddr->err_int_en = 0x0000000d;
+ ddr->err_disable = 0x00000000;
+ ddr->err_sbe = 0x00010000;
+#endif
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+ udelay(1000);
+
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return 512 * 1024 * 1024;
+#endif
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+ PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
+ {}
+};
+#endif
+
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+config_table:pci_mpc86xxcts_config_table
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+int first_free_busno = 0;
+
+void pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+
+#ifdef CONFIG_PCIE1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_configured = (io_sel == 1) || (io_sel == 4);
+ int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
+ (host_agent == 5);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
+ printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det)
+ pci->pme_msg_det = 0xffffffff;
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCI-Express 1 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+
+ } else
+ puts(" PCI-Express 1: Disabled\n");
+ }
+#else
+ puts("PCI-Express 1: Disabled\n");
+#endif /* CONFIG_PCIE1 */
+
+
+#ifdef CONFIG_PCIE2
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie2_hose;
+
+ int pcie_configured = (io_sel == 0) || (io_sel == 4);
+ int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
+ (host_agent == 4);
+
+ if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
+ printf(" PCI-Express 2 connected to slot as %s" \
+ " (base address %x)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det)
+ pci->pme_msg_det = 0xffffffff;
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE2_MEM_BASE,
+ CFG_PCIE2_MEM_PHYS,
+ CFG_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE2_IO_BASE,
+ CFG_PCIE2_IO_PHYS,
+ CFG_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCI-Express 2 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ } else
+ puts(" PCI-Express 2: Disabled\n");
+ }
+#else
+ puts("PCI-Express 2: Disabled\n");
+#endif /* CONFIG_PCIE2 */
+
+
+#ifdef CONFIG_PCI1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+
+ if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
+ printf(" PCI connected to PCI slots as %s" \
+ " (base address %x)\n",
+ pci_agent ? "Agent" : "Host",
+ (uint)pci);
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr,
+ (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCI on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+
+
+ } else
+ puts(" PCI: Disabled\n");
+ }
+#endif /* CONFIG_PCI1 */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+
+#ifdef CONFIG_PCI1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+
+}
+#endif
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+ ulong a;
+
+ a = PIXIS_BASE + PIXIS_SPD;
+ i = in8(a);
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333000;
+ break;
+ case 1:
+ val = 39999600;
+ break;
+ case 2:
+ val = 49999500;
+ break;
+ case 3:
+ val = 66666000;
+ break;
+ case 4:
+ val = 83332500;
+ break;
+ case 5:
+ val = 99999000;
+ break;
+ case 6:
+ val = 133332000;
+ break;
+ case 7:
+ val = 166665000;
+ break;
+ }
+
+ return val;
+}
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
new file mode 100644
index 0000000..b70637f
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_FSL_DIU_FB
+
+#include "../common/pixis.h"
+#include "../common/fsl_diu_fb.h"
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
+
+extern unsigned int FSL_Logo_BMP[];
+
+static int xres, yres;
+
+
+void mpc8610hpcd_diu_init(void)
+{
+ char *monitor_port;
+ int gamma_fix;
+ unsigned int pixel_format;
+ unsigned char tmp_val;
+ unsigned char pixis_arch;
+
+ tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
+ pixis_arch = in8(PIXIS_BASE + PIXIS_VER);
+
+ monitor_port = getenv("monitor");
+ if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */
+ xres = 1280;
+ yres = 1024;
+ if (pixis_arch == 0x01)
+ pixel_format = 0x88882317;
+ else
+ pixel_format = 0x88883316;
+ gamma_fix = 0;
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+
+ } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+ xres = 1024;
+ yres = 768;
+ pixel_format = 0x88883316;
+ gamma_fix = 0;
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
+
+ } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
+ xres = 1280;
+ yres = 1024;
+ pixel_format = 0x88883316;
+ gamma_fix = 1;
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7);
+
+ } else { /* DVI */
+ xres = 1280;
+ yres = 1024;
+ pixel_format = 0x88882317;
+ gamma_fix = 0;
+ out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08);
+ }
+
+ fsl_diu_init(xres, pixel_format, gamma_fix,
+ (unsigned char *)FSL_Logo_BMP);
+}
+
+int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[])
+{
+ unsigned int addr;
+
+ if (argc < 2) {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (!strncmp(argv[1],"init",4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+ fsl_diu_clear_screen();
+ drv_video_init();
+#else
+ mpc8610hpcd_diu_init();
+#endif
+ } else {
+ addr = simple_strtoul(argv[1], NULL, 16);
+ fsl_diu_clear_screen();
+ fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
+ "diufb init | addr - Init or Display BMP file\n",
+ "init\n - initialize DIU\n"
+ "addr\n - display bmp at address 'addr'\n"
+ );
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+ GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+ struct fb_info *info;
+
+ mpc8610hpcd_diu_init();
+
+ /* fill in Graphic device struct */
+ sprintf(pGD->modeIdent,
+ "%dx%dx%d %ldkHz %ldHz",
+ xres, yres, 32, 64, 60);
+
+ pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+ pGD->winSizeX = xres;
+ pGD->winSizeY = yres - info->logo_height;
+ pGD->plnSizeX = pGD->winSizeX;
+ pGD->plnSizeY = pGD->winSizeY;
+
+ pGD->gdfBytesPP = 4;
+ pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+ pGD->isaBase = 0;
+ pGD->pciBase = 0;
+ pGD->memSize = info->screen_size - info->logo_size;
+
+ /* Cursor Start Address */
+ pGD->dprBase = 0;
+ pGD->vprBase = 0;
+ pGD->cprBase = 0;
+
+ return (void *)pGD;
+}
+
+void video_set_lut (unsigned int index, /* color number */
+ unsigned char r, /* red */
+ unsigned char g, /* green */
+ unsigned char b /* blue */
+ )
+{
+ return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
+
+#endif /* CONFIG_FSL_DIU_FB */
diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds
new file mode 100644
index 0000000..ae9c6c4
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+
+ /* Read-only sections, merged into text segment: */
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc86xx/start.o (.text)
+ board/freescale/mpc8610hpcd/init.o (.bootpg)
+ cpu/mpc86xx/traps.o (.text)
+ cpu/mpc86xx/interrupts.o (.text)
+ cpu/mpc86xx/cpu_init.o (.text)
+ cpu/mpc86xx/cpu.o (.text)
+ cpu/mpc86xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 931be9f..8278789 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -27,11 +27,8 @@
#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <asm/io.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
+#include <libfdt.h>
+#include <fdt_support.h>
#include "../common/pixis.h"
@@ -324,36 +321,47 @@ void pci_init_board(void)
}
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
- u32 *p;
- int len;
+ int node, tmp[2];
+ const char *path;
- ft_cpu_setup(blob, bd);
+ fdt_fixup_ethernet(blob, bd);
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", bd->bi_busfreq / 4, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "clock-frequency", bd->bi_intfreq, 1);
+ do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+ "bus-frequency", bd->bi_busfreq, 1);
+
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", bd->bi_busfreq, 1);
+
+ fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
#ifdef CONFIG_PCI1
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@8000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
#ifdef CONFIG_PCI2
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
- if (p != NULL) {
- p[0] = 0;
- p[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
- }
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
#endif
+ }
}
#endif