Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

17 files changed, 258 insertions, 101 deletions

diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 6e64745..db0cf28 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -13,10 +13,10 @@
 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
 				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
 
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
 				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
 				{7, 8}, {9, 0}, {2, 14}, {12, 15},
 				{-1, -1}, {-1, -1} };
 
@@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
 				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
@@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
 				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
 
-static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
+static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
 				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 
-static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
 				{7, 8}, {1, 9}, {14, 3}, {15, 12},
 				{-1, -1}, {-1, -1} };
 
@@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
 				{-1, -1}, {-1, -1} };
 
 #ifdef CONFIG_PPC_B4420
-static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
 
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 457d1ad..f9550c4 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -45,9 +45,7 @@ COBJS-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
 
 COBJS-$(CONFIG_MPC8536DS)	+= ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
-ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
-endif
 COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c
index 8a3dc33..97a25e8 100644
--- a/board/freescale/common/vsc3316_3308.c
+++ b/board/freescale/common/vsc3316_3308.c
@@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr)
 	return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
 }
 
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
 		unsigned int num_con)
 {
 	unsigned int i;
diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h
index 4003fcd..2a49187 100644
--- a/board/freescale/common/vsc3316_3308.h
+++ b/board/freescale/common/vsc3316_3308.h
@@ -12,7 +12,7 @@
 #include <errno.h>
 
 int vsc_if_enable(unsigned int vsc_addr);
-int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
 		unsigned int num_con);
 int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
 		unsigned int num_con);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 7a84cd2..2fb4037 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -68,7 +68,7 @@ local_bus_init(void)
 
 	get_sys_info(&sysinfo);
 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
 		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 3d2dabd..1e21a66 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -250,7 +250,7 @@ local_bus_init(void)
 
 	get_sys_info(&sysinfo);
 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
 		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index d4e7abe..ee92695 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -248,7 +248,7 @@ local_bus_init(void)
 
 	get_sys_info(&sysinfo);
 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
 		lbc->lcrr |= LCRR_DBYP;	/* DLL Bypass */
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index a45a558..162636e 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -273,7 +273,7 @@ local_bus_init(void)
 
 	get_sys_info(&sysinfo);
 	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
 		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index 73289f3..d0e712e 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -26,7 +26,7 @@ void sdram_init(void)
 
 	ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
 	ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
+	ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000;
 
 	/* mask off E bit */
 	u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index cfc05f7..3bc4f43 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -21,6 +21,9 @@ ifdef MINIMAL
 COBJS-y        += spl_minimal.o tlb.o law.o
 
 else
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= ddr.o
 COBJS-y	+= law.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644
index 0000000..b9dbf81
--- /dev/null
+++ b/board/freescale/p1022ds/spl.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/ngpixis.h"
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+ulong get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	int px_spd;
+	u32 plat_ratio, sys_clk, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		     in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+#ifdef CONFIG_SPL_SPI_BOOT
+	/* Enable the SPI */
+	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+
+	/* initialize selected port with appropriate baud rate */
+	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	bus_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+#endif
+	/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#else
+	env_relocate();
+#endif
+
+	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+	puts("Tertiary program loader running in sram...");
+#else
+	puts("Second program loader running in sram...\n");
+#endif
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index d150d95..8b34396 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -12,51 +12,6 @@
 #include <asm/fsl_ddr_sdram.h>
 
 
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
-	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
-			&ddr->sdram_cfg);
-
-	in_be32(&ddr->sdram_cfg);
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-	in_be32(&ddr->sdram_cfg);
-
-	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
 const static u32 sysclk_tbl[] = {
 	66666000, 7499900, 83332500, 8999900,
 	99999000, 11111000, 12499800, 13333200
@@ -68,6 +23,10 @@ void board_init_f(ulong bootflag)
 	u32 plat_ratio, sys_clk, bus_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+	set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+	set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
 	/* for FPGA */
 	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
 	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -83,9 +42,6 @@ void board_init_f(ulong bootflag)
 
 	puts("\nNAND boot... ");
 
-	/* Initialize the DDR3 */
-	sdram_init();
-
 	/* copy code to RAM and jump to it - this should not return */
 	/* NOTE - code has to be copied out of NAND buffer before
 	 * other blocks can be read.
@@ -96,6 +52,7 @@ void board_init_f(ulong bootflag)
 
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
+	puts("\nSecond program loader running in sram...");
 	nand_boot();
 }
 
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index 2eef6ad..e7ae2e2 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_4K, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if defined(CONFIG_SYS_RAMBOOT) || \
+	(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
 	/* **** - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 8, BOOKE_PAGESZ_1G, 1),
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 8, BOOKE_PAGESZ_1G, 1),
 	/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 9, BOOKE_PAGESZ_1G, 1),
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 
 #ifdef CONFIG_SYS_NAND_BASE
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 10, BOOKE_PAGESZ_16K, 1),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16K, 1),
 #endif
 
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		      0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 5c51845..c0b72e0 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -247,7 +247,7 @@ phys_size_t fixed_sdram(void)
 
 	get_sys_info(&sysinfo);
 	printf("Configuring DDR for %s MT/s data rate\n",
-			strmhz(buf, sysinfo.freqDDRBus));
+			strmhz(buf, sysinfo.freq_ddrbus));
 
 	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 697c0dd..67f69d7 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -53,7 +53,7 @@ phys_size_t fixed_sdram(void)
 
 	get_sys_info(&sysinfo);
 	printf("Configuring DDR for %s MT/s data rate\n",
-			strmhz(buf, sysinfo.freqDDRBus));
+			strmhz(buf, sysinfo.freq_ddrbus));
 
 	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index c771e17..b5f488b 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -172,7 +172,10 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 				enum fm_port port, int offset)
 {
-	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+	int interface = fm_info_get_enet_if(port);
+
+	if (interface == PHY_INTERFACE_MODE_SGMII ||
+	    interface == PHY_INTERFACE_MODE_QSGMII) {
 		switch (port) {
 		case FM1_DTSEC1:
 			if (qsgmiiphy_fix[port])
@@ -272,6 +275,7 @@ void fdt_fixup_board_enet(void *fdt)
 	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
 			switch (mdio_mux[i]) {
 			case EMI1_SLOT1:
 				fdt_status_okay_by_alias(fdt, "emi1_slot1");
@@ -393,7 +397,7 @@ static void initialize_qsgmiiphy_fix(void)
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
-	int i, idx, lane, slot;
+	int i, idx, lane, slot, interface;
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -470,9 +474,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC9,
-						slot_qsgmii_phyaddr[1][3]);
-			fm_info_set_phy_address(FM1_DTSEC10,
 						slot_qsgmii_phyaddr[1][2]);
+			fm_info_set_phy_address(FM1_DTSEC10,
+						slot_qsgmii_phyaddr[1][3]);
 		}
 		break;
 	case 40:
@@ -482,9 +486,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC10,
-						slot_qsgmii_phyaddr[1][3]);
-			fm_info_set_phy_address(FM1_DTSEC9,
 						slot_qsgmii_phyaddr[1][2]);
+			fm_info_set_phy_address(FM1_DTSEC9,
+						slot_qsgmii_phyaddr[1][3]);
 		}
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -498,15 +502,31 @@ int board_eth_init(bd_t *bis)
 
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		idx = i - FM1_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
 		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_1,
+		case PHY_INTERFACE_MODE_QSGMII:
+			if (interface == PHY_INTERFACE_MODE_QSGMII) {
+				if (idx <= 3)
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+							QSGMII_FM1_A);
+				else
+					lane = serdes_get_first_lane(FSL_SRDS_1,
+							QSGMII_FM1_B);
+				if (lane < 0)
+					break;
+				slot = lane_to_slot_fsm1[lane];
+				debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
+				      idx + 1, slot);
+			} else {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
 						SGMII_FM1_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot_fsm1[lane];
-			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
-				idx + 1, slot);
+				if (lane < 0)
+					break;
+				slot = lane_to_slot_fsm1[lane];
+				debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+				      idx + 1, slot);
+			}
 			if (QIXIS_READ(present2) & (1 << (slot - 1)))
 				fm_disable_port(i);
 			switch (slot) {
@@ -600,8 +620,8 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
 		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
-		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
-		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 		break;
 	case 40:
 	case 46:
@@ -641,15 +661,31 @@ int board_eth_init(bd_t *bis)
 
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 		idx = i - FM2_DTSEC1;
-		switch (fm_info_get_enet_if(i)) {
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
 		case PHY_INTERFACE_MODE_SGMII:
-			lane = serdes_get_first_lane(FSL_SRDS_2,
+		case PHY_INTERFACE_MODE_QSGMII:
+			if (interface == PHY_INTERFACE_MODE_QSGMII) {
+				if (idx <= 3)
+					lane = serdes_get_first_lane(FSL_SRDS_2,
+							QSGMII_FM2_A);
+				else
+					lane = serdes_get_first_lane(FSL_SRDS_2,
+							QSGMII_FM2_B);
+				if (lane < 0)
+					break;
+				slot = lane_to_slot_fsm2[lane];
+				debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
+				      idx + 1, slot);
+			} else {
+				lane = serdes_get_first_lane(FSL_SRDS_2,
 						SGMII_FM2_DTSEC1 + idx);
-			if (lane < 0)
-				break;
-			slot = lane_to_slot_fsm2[lane];
-			debug("FM2@DTSEC%u expects SGMII in slot %u\n",
-				idx + 1, slot);
+				if (lane < 0)
+					break;
+				slot = lane_to_slot_fsm2[lane];
+				debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+				      idx + 1, slot);
+			}
 			if (QIXIS_READ(present2) & (1 << (slot - 1)))
 				fm_disable_port(i);
 			switch (slot) {
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f54..0c1a4fb 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
 				{8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
 				{10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
 				{10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
 				{8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
@@ -353,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void)
 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-	if (srds_prtcl_s1) {
+	switch (srds_prtcl_s1) {
+	case 38:
+		/* swap first lane and third lane on slot1 */
+		vsc3316_fsm1_tx[0][1] = 14;
+		vsc3316_fsm1_tx[6][1] = 0;
+		vsc3316_fsm1_rx[1][1] = 2;
+		vsc3316_fsm1_rx[6][1] = 13;
+	case 40:
+	case 46:
+	case 48:
+		/* swap first lane and third lane on slot2 */
+		vsc3316_fsm1_tx[2][1] = 8;
+		vsc3316_fsm1_tx[4][1] = 6;
+		vsc3316_fsm1_rx[2][1] = 10;
+		vsc3316_fsm1_rx[5][1] = 5;
+	default:
 		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
 		if (ret)
 			return ret;
 		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
 		if (ret)
 			return ret;
+		break;
 	}
 
 	srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-	if (srds_prtcl_s2) {
+	switch (srds_prtcl_s2) {
+	case 38:
+		/* swap first lane and third lane on slot3 */
+		vsc3316_fsm2_tx[2][1] = 11;
+		vsc3316_fsm2_tx[5][1] = 4;
+		vsc3316_fsm2_rx[2][1] = 9;
+		vsc3316_fsm2_rx[4][1] = 7;
+	case 40:
+	case 46:
+	case 48:
+	case 50:
+	case 52:
+	case 54:
+		/* swap first lane and third lane on slot4 */
+		vsc3316_fsm2_tx[6][1] = 3;
+		vsc3316_fsm2_tx[1][1] = 12;
+		vsc3316_fsm2_rx[0][1] = 1;
+		vsc3316_fsm2_rx[6][1] = 15;
+	default:
 		ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
 		if (ret)
 			return ret;
 		ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
 		if (ret)
 			return ret;
+		break;
 	}
 
 	return 0;