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authorAnton Vorontsov <avorontsov@ru.mvista.com>2007-10-22 19:58:19 +0400
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-01-09 16:25:03 -0600
commit64d4bcb087c2ece1c4d0de8efe85e0075e5b1594 (patch)
tree39d81e6acd3d24877e6246c7f18c9158251ca9dc /board/freescale
parentad162249cb371e9e38971676f09be791e5f3cf4a (diff)
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MPC8568E-MDS: set up QE pario for UART1
To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should be set up appropriately. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 1aaecf3..3c3726b 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -87,6 +87,13 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{1, 31, 2, 0, 3}, /* GTX125 */
{4, 6, 3, 0, 2}, /* MDIO */
{4, 5, 1, 0, 2}, /* MDC */
+
+ /* UART1 */
+ {2, 0, 1, 0, 2}, /* UART_SOUT1 */
+ {2, 1, 1, 0, 2}, /* UART_RTS1 */
+ {2, 2, 2, 0, 2}, /* UART_CTS1 */
+ {2, 3, 2, 0, 2}, /* UART_SIN1 */
+
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};