ENGR00315894-54 iMX6SX/SL: Modify SOC to support two ENET

iMX6SX has different enet system clocks with iMX6SL, and has two ENET
controllers. So update clocks and soc APIs accordingly to support this
features.

1. Modify the clock API "enable_enet_clock" to enable enet system clock
   for enet controllers.
2. Enet RGMII TX clock source may come from external or internal PLL.
   By default, use the external phy CLK_25M output as TX clock source.
   When using internal PLL as source, the function enable_fec_anatop_clock
   must be called to enable clock for each enet controller.
3. Modify the MAC address function "imx_get_mac_from_fuse" to get either
   ENET MAC address.
4. Add configuration "CONFIG_FEC_MXC_25M_REF_CLK" to enable ENET 25Mhz
   reference clock.
5. Modify imx6slevk BSP to fit the new APIs.

Signed-off-by: Fugang Duan  <B38611@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index d4486ed..1667ada 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -608,7 +608,7 @@ static int setup_fec(void)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	ret = enable_fec_anatop_clock(ENET_50MHz);
+	ret = enable_fec_anatop_clock(0, ENET_50MHz);
 	if (ret)
 		return ret;