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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-06-18 19:27:23 -0500
committerJohn Rigby <jrigby@freescale.com>2008-07-11 10:45:58 -0600
commitab4860b255239dbaecccdd002c8d11f4ef54dd75 (patch)
tree689796916df50e0c293e3414c701164fce074d28 /board/freescale
parentdd08e97361fbc9e79fa5ef1a8acf29273b934b11 (diff)
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ColdFire: Fix power up issue for MCF5235
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/m5235evb/m5235evb.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8..bd8a4e5 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
sdram->dacr0 =
SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ asm("nop");
/* Initialize DMR0 */
sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ asm("nop");
/* Set IP (bit 3) in DACR */
sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
/* Finish the configuration by issuing the MRS. */
sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ asm("nop");
/* Write to the SDRAM Mode Register */
*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;