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authorStefano Babic <sbabic@denx.de>2013-02-23 10:13:40 +0100
committerStefano Babic <sbabic@denx.de>2013-02-23 10:13:40 +0100
commit9cd9b34dc7f247fd0fce08ab688bf8197f1bfdbc (patch)
tree89561497322fff78d3d2e4a8e736f18ab4e0ddfb /board/freescale
parentbec0160e9f5adab1d451ded3a95b0114b14e1970 (diff)
parenta5627914daad144727655a72bd3c8a8958fbcdcf (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/b4860qds/Makefile54
-rw-r--r--board/freescale/b4860qds/b4860qds.c505
-rw-r--r--board/freescale/b4860qds/b4860qds.h26
-rw-r--r--board/freescale/b4860qds/b4860qds_crossbar_con.h67
-rw-r--r--board/freescale/b4860qds/b4860qds_qixis.h37
-rw-r--r--board/freescale/b4860qds/ddr.c190
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c338
-rw-r--r--board/freescale/b4860qds/law.c44
-rw-r--r--board/freescale/b4860qds/pci.c39
-rw-r--r--board/freescale/b4860qds/tlb.c127
-rw-r--r--board/freescale/bsc9131rdb/bsc9131rdb.c2
-rw-r--r--board/freescale/bsc9132qds/Makefile52
-rw-r--r--board/freescale/bsc9132qds/README150
-rw-r--r--board/freescale/bsc9132qds/bsc9132qds.c403
-rw-r--r--board/freescale/bsc9132qds/ddr.c209
-rw-r--r--board/freescale/bsc9132qds/law.c35
-rw-r--r--board/freescale/bsc9132qds/tlb.c92
-rw-r--r--board/freescale/common/qixis.c107
-rw-r--r--board/freescale/common/qixis.h13
-rw-r--r--board/freescale/corenet_ds/corenet_ds.c2
-rw-r--r--board/freescale/corenet_ds/rcw_p2041rdb.cfg11
-rw-r--r--board/freescale/mpc8313erdb/mpc8313erdb.c10
-rw-r--r--board/freescale/p1010rdb/ddr.c6
-rw-r--r--board/freescale/p1010rdb/p1010rdb.c6
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c2
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c2
-rw-r--r--board/freescale/p2041rdb/eth.c39
-rw-r--r--board/freescale/p2041rdb/p2041rdb.c46
-rw-r--r--board/freescale/t4qds/law.c2
-rw-r--r--board/freescale/t4qds/t4qds.c85
-rw-r--r--board/freescale/t4qds/t4qds.h11
-rw-r--r--board/freescale/t4qds/tlb.c2
32 files changed, 2631 insertions, 83 deletions
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
new file mode 100644
index 0000000..06018f4
--- /dev/null
+++ b/board/freescale/b4860qds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
new file mode 100644
index 0000000..41887c2
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "b4860qds.h"
+#include "b4860qds_qixis.h"
+#include "b4860qds_crossbar_con.h"
+
+#define CLK_MUX_SEL_MASK 0x4
+#define ETH_PHY_CLK_OUT 0x4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
+ static const char *const freq[] = {"100", "125", "156.25", "161.13",
+ "122.88", "122.88", "122.88"};
+ int clock;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw >= 0x8 && sw <= 0xE)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 5) & 7;
+ printf("Bank1=%sMHz ", freq[clock]);
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = (sw >> 6) & 3;
+ printf("Bank2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca(u8 ch)
+{
+ int ret;
+
+ /* Selecting proper channel via PCA*/
+ ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
+ if (ret) {
+ printf("PCA: failed to select proper channel.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int configure_vsc3316_3308(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int num_vsc16_con, num_vsc08_con;
+ u32 serdes1_prtcl, serdes2_prtcl;
+ int ret;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ switch (serdes1_prtcl) {
+ case 0x2a:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B: SGMII
+ * Lanes: C,D,E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
+#ifdef CONFIG_PPC_B4420
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+#endif
+
+ case 0x3E:
+ case 0x0D:
+ case 0x0E:
+ case 0x12:
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for:%x"
+ " SerDes1 Protocol.\n", serdes1_prtcl);
+ return -1;
+ }
+
+ switch (serdes2_prtcl) {
+ case 0x9E:
+ case 0x9A:
+ case 0x98:
+ case 0xb2:
+ case 0x49:
+ case 0x4E:
+ case 0x8D:
+ case 0x7A:
+ num_vsc08_con = NUM_CON_VSC3308;
+ /* Configure VSC3308 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+ if (!ret) {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for: %x"
+ " SerDes2 Protocol.\n", serdes2_prtcl);
+ return -1;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Configure VSC3316 and VSC3308 crossbar switches */
+ if (configure_vsc3316_3308())
+ printf("VSC:failed to configure VSC3316/3308.\n");
+ else
+ printf("VSC:VSC3316/3308 successfully configured.\n");
+
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+static int serdes_refclock(u8 sw, u8 sdclk)
+{
+ unsigned int clock;
+ int ret = -1;
+ u8 brdcfg4;
+
+ if (sdclk == 1) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
+ return SRDS_PLLCR0_RFCK_SEL_125;
+ else
+ clock = (sw >> 5) & 7;
+ } else
+ clock = (sw >> 6) & 3;
+
+ switch (clock) {
+ case 0:
+ ret = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ ret = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ ret = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ case 3:
+ ret = SRDS_PLLCR0_RFCK_SEL_161_13;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ ret = SRDS_PLLCR0_RFCK_SEL_122_88;
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.13";
+ default:
+ return "122.88";
+ }
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ u8 sw;
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ int clock;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = serdes_refclock(sw, 1);
+ if (clock >= 0)
+ actual[0] = clock;
+ else
+ printf("Warning: SDREFCLK1 switch setting is unsupported\n");
+
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = serdes_refclock(sw, 2);
+ if (clock >= 0)
+ actual[1] = clock;
+ else
+ printf("Warning: SDREFCLK2 switch setting unsupported\n");
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 pllcr0 = srds_regs->bank[i].pllcr0;
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * Dump board switch settings.
+ * The bits that cannot be read/sampled via some FPGA or some
+ * registers, they will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[5];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
+ (brdcfg[9] & 0x08);
+ sw[1] = ((dutcfg[1] & 0x01) << 7) | \
+ ((dutcfg[2] & 0x07) << 4) | \
+ ((dutcfg[6] & 0x10) >> 1) | \
+ ((dutcfg[6] & 0x80) >> 5) | \
+ ((dutcfg[1] & 0x40) >> 5) | \
+ (dutcfg[6] & 0x01);
+ sw[2] = dutcfg[0];
+ sw[3] = 0;
+ sw[4] = ((brdcfg[1] & 0x30) << 2) | \
+ ((brdcfg[1] & 0xc0) >> 2) | \
+ (brdcfg[1] & 0x0f);
+
+ puts("DIP switch settings:\n");
+ for (i = 0; i < 5; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
new file mode 100644
index 0000000..f290f3c
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
new file mode 100644
index 0000000..994dec5
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_CONNECTIONS_H__
+#define __CROSSBAR_CONNECTIONS_H__
+
+#define NUM_CON_VSC3316 8
+#define NUM_CON_VSC3308 4
+
+static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
+ {5, 11}, {4, 5}, {2, 6}, {12, 9} };
+
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
+ {5, 15}, {4, 14}, {2, 12}, {12, 13} };
+
+static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
+ {11, 11}, {5, 10}, {6, 3}, {9, 12} };
+
+static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+
+static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
+
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+
+static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
+
+static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
new file mode 100644
index 0000000..575b2ae
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __B4860QDS_QIXIS_H__
+#define __B4860QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for B4860QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* CLK */
+#define QIXIS_CLK_66 0x0
+#define QIXIS_CLK_100 0x1
+#define QIXIS_CLK_125 0x2
+#define QIXIS_CLK_133 0x3
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
new file mode 100644
index 0000000..dd4c0f6
--- /dev/null
+++ b/board/freescale/b4860qds/ddr.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1071,
+ .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
+ .tAA_ps = 13910,
+ .tWR_ps = 15000,
+ .tRCD_ps = 13910,
+ .tRRD_ps = 6000,
+ .tRP_ps = 13910,
+ .tRAS_ps = 34000,
+ .tRC_ps = 48910,
+ .tRFC_ps = 260000,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 35000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
new file mode 100644
index 0000000..68e2725
--- /dev/null
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Author: Sandeep Kumar Singh <sandeep@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
+ * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
+ * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
+ * one Fman device on B4860. The SERDES configuration is used to determine
+ * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
+ * to which PHYs. So for a given Fman MAC, there is one and only PHY it
+ * connects to. MACs cannot be routed to PHYs dynamically. This configuration
+ * is done at boot time by reading SERDES protocol from RCW.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+
+#ifdef CONFIG_FMAN_ENET
+
+/*
+ * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
+ * lane at index is mapped to slot number n. A value of '0' will mean
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0
+};
+
+/*
+ * This function initializes the lane_to_slot[] array. It reads RCW to check
+ * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
+ * lane_to_slot[] accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ unsigned int serdes2_prtcl;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Initializing lane to slot: Serdes2 protocol: %x\n",
+ serdes2_prtcl);
+
+ switch (serdes2_prtcl) {
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F: Aur
+ * Lanes: G,H: SRIO
+ */
+ case 0x91:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x93:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x98:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: XAUI2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9a:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: PCI
+ * Lanes: C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9e:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0xb2:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F: SGMII 3&4
+ * Lanes: G,H: XFI
+ */
+ case 0xc2:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ lane_to_slot[12] = 2;
+ lane_to_slot[13] = lane_to_slot[12];
+ lane_to_slot[14] = lane_to_slot[12];
+ lane_to_slot[15] = lane_to_slot[12];
+ break;
+
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+ return;
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ struct memac_mdio_info tg_memac_mdio_info;
+ unsigned int i;
+ unsigned int serdes1_prtcl, serdes2_prtcl;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ tg_memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tg_memac_mdio_info);
+
+ /*
+ * Program the two on board DTSEC PHY addresses assuming that they are
+ * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
+ * 6 to on board SGMII phys
+ */
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+
+ switch (serdes1_prtcl) {
+ case 0x2a:
+ /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
+ debug("Setting phy addresses for FM1_DTSEC5: %x and"
+ "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ /* Fixing Serdes clock by programming FPGA register */
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ break;
+#ifdef CONFIG_PPC_B4420
+ case 0x18:
+ /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
+ debug("Setting phy addresses for FM1_DTSEC3: %x and"
+ "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ /* Fixing Serdes clock by programming FPGA register */
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ break;
+#endif
+ default:
+ printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+ switch (serdes2_prtcl) {
+ case 0x18:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
+ break;
+ case 0x49:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ break;
+ case 0x8d:
+ case 0xb2:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ break;
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[32];
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+
+ sprintf(alias, "phy_sgmii_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ char alias[32];
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_NONE:
+ sprintf(alias, "ethernet%u", i);
+ fdt_status_disabled_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
+ }
+}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
new file mode 100644
index 0000000..4142e01
--- /dev/null
+++ b/board/freescale/b4860qds/law.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
new file mode 100644
index 0000000..b130d13
--- /dev/null
+++ b/board/freescale/b4860qds/pci.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
new file mode 100644
index 0000000..373cb78
--- /dev/null
+++ b/board/freescale/b4860qds/tlb.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_64K, 1),
+#endif
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 2e0e55f..fe870b6 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -59,7 +59,7 @@ int checkboard(void)
{
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
new file mode 100644
index 0000000..267400b
--- /dev/null
+++ b/board/freescale/bsc9132qds/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
new file mode 100644
index 0000000..4a3dbfe
--- /dev/null
+++ b/board/freescale/bsc9132qds/README
@@ -0,0 +1,150 @@
+Overview
+--------
+ The BSC9132 is a highly integrated device that targets the evolving
+ Microcell, Picocell, and Enterprise-Femto base station market subsegments.
+
+ The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
+ core technologies with MAPLE-B2P baseband acceleration processing elements
+ to address the need for a high performance, low cost, integrated solution
+ that handles all required processing layers without the need for an
+ external device except for an RF transceiver or, in a Micro base station
+ configuration, a host device that handles the L3/L4 and handover between
+ sectors.
+
+ The BSC9132 SoC includes the following function and features:
+ - Power Architecture subsystem including two e500 processors with
+ 512-Kbyte shared L2 cache
+ - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
+ cache
+ - 32 Kbyte of shared M3 memory
+ - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
+ Processing (MAPLE-B2P)
+ - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
+ ECC), up to 1333 MHz data rate
+ - Dedicated security engine featuring trusted boot
+ - Two DMA controllers
+ - OCNDMA with four bidirectional channels
+ - SysDMA with sixteen bidirectional channels
+ - Interfaces
+ - Four-lane SerDes PHY
+ - PCI Express controller complies with the PEX Specification-Rev 2.0
+ - Two Common Public Radio Interface (CPRI) controller lanes
+ - High-speed USB 2.0 host and device controller with ULPI interface
+ - Enhanced secure digital (SD/MMC) host controller (eSDHC)
+ - Antenna interface controller (AIC), supporting four industry
+ standard JESD207/four custom ADI RF interfaces
+ - ADI lanes support both full duplex FDD support & half duplex TDD
+ - Universal Subscriber Identity Module (USIM) interface that
+ facilitates communication to SIM cards or Eurochip pre-paid phone
+ cards
+ - Two DUART, two eSPI, and two I2C controllers
+ - Integrated Flash memory controller (IFC)
+ - GPIO
+ - Sixteen 32-bit timers
+
+The SC3850 core subsystem consists of the following:
+ - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
+ - 32 KB, 8-way, level 1 data cache (L1 DCache)
+ - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
+ - Memory management unit (MMU)
+ - Global interrupt controller ( GIC)
+ - Debug and profiling unit (DPU)
+ - Two 32-bit quad timers
+
+BSC9132QDS board Overview
+-------------------------
+ 2Gbyte DDR3 (on board DDR), Dual Ranki
+ 32Mbyte 16bit NOR flash
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ SD slot
+ USB-ULPI
+ eTSEC1: Connected to SGMII PHY
+ eTSEC2: Connected to SGMII PHY
+ PCIe
+ CPRI
+ SerDes
+ I2C RTC
+ DUART interface: supports one UARTs up to 115200 bps for console display
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
+ (SYSCLK = 100MHz, DDRCLK = 100MHz)
+2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
+ (SYSCLK = 100MHz, DDRCLK = 133MHz)
+
+Boot Methods Supported
+-----------------------
+1. NOR Flash
+2. NAND Flash
+3. SD Card
+4. SPI flash
+
+Default Boot Method
+--------------------
+NOR boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9132QDS:
+1. NOR Flash
+ make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
+2. NAND Flash : It is currently not supported
+3. SPI Flash
+ make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
+4. SD Card
+ make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
+
+Memory map
+-----------
+ 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
+ 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
+ 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
+ 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
+ 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
+ 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
+ 0xC000_0000 0xC000_7FFF M3 Memory 32K
+ 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
+ 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
+ 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
+ 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
+ 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
+ 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
+ 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
+ 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 100000
+ nand write 1000000 0 100000
+ reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 bsc9132qds.dtb
+ bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
new file mode 100644
index 0000000..6e1b558
--- /dev/null
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <asm/fsl_ifc.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#endif
+
+#include "../common/qixis.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+ switch (srds_cfg) {
+ /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x03);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 CPRI 1 */
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ case 27:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x01);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 SGMII2 */
+ case 11:
+ case 32:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x00);
+ break;
+
+ /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x07);
+ break;
+
+ /* PEX(1) SGMII2 SGMII1 CPRI 1 */
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 38:
+ case 39:
+ case 40:
+ case 41:
+ case 42:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x05);
+ break;
+
+ /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
+ case 43:
+ case 44:
+ case 45:
+ case 46:
+ case 47:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
+ break;
+
+
+ default:
+ break;
+ }
+}
+
+int board_early_init_r(void)
+{
+#ifndef CONFIG_SYS_NO_FLASH
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+ set_tlb(1, flashbase + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
+#endif
+ board_config_serdes_mux();
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int checkboard(void)
+{
+ struct cpu_type *cpu;
+ u8 sw;
+
+ cpu = gd->arch.cpu;
+ printf("Board: %sQDS\n", cpu->name);
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
+ QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ printf("IFC chip select:");
+ switch (sw) {
+ case 0:
+ printf("NOR\n");
+ break;
+ case 2:
+ printf("Promjet\n");
+ break;
+ case 4:
+ printf("NAND\n");
+ break;
+ default:
+ printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+
+#endif
+
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+ tsec_eth_init(bis, tsec_info, num);
+
+ #ifdef CONFIG_PCI
+ pci_eth_init(bis);
+ #endif
+
+ return 0;
+}
+#endif
+
+#define USBMUX_SEL_MASK 0xc0
+#define USBMUX_SEL_UART2 0xc0
+#define USBMUX_SEL_USB 0x40
+#define SPIMUX_SEL_UART3 0x80
+#define GPS_MUX_SEL_GPS 0x40
+
+#define TSEC_1588_CLKIN_MASK 0x03
+#define CON_XCVR_REF_CLK 0x00
+
+int misc_init_r(void)
+{
+ u8 val;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ /*Configure 1588 clock-in source from RF Card*/
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
+
+ if (hwconfig("uart2") && hwconfig("usb1")) {
+ printf("UART2 and USB cannot work together on the board\n");
+ printf("Remove one from hwconfig and reset\n");
+ } else {
+ if (hwconfig("uart2")) {
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_USB_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
+ } else {
+ /* By default USB should be selected.
+ * Programming FPGA to select USB. */
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
+ }
+
+ }
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
+ clrbits_be32(&gur->pmuxcr,
+ MPC85xx_PMUXCR0_SIM_SEL_MASK);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* UART3 and SPI1 (Flashes) are muxed together */
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_UART3_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
+
+ /* MUX to select UART3 connection to J24 header
+ * or to GPS */
+ val = QIXIS_READ_I2C(brdcfg[6]);
+ if (hwconfig("gps"))
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val | GPS_MUX_SEL_GPS));
+ else
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val & ~(GPS_MUX_SEL_GPS)));
+ }
+ }
+ return 0;
+}
+
+void fdt_del_node_compat(void *blob, const char *compatible)
+{
+ int err;
+ int off = fdt_node_offset_by_compatible(blob, -1, compatible);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ compatible, fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ compatible, fdt_strerror(err));
+ }
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ #if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+ #endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ if (!(hwconfig("uart2") && hwconfig("usb1"))) {
+ /* If uart2 is there in hwconfig remove usb node from
+ * device tree */
+
+ if (hwconfig("uart2")) {
+ /* remove dts usb node */
+ fdt_del_node_compat(blob, "fsl-usb2-dr");
+ } else {
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_del_node_and_alias(blob, "serial2");
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC)
+ /* Delete SPI node from the device tree */
+ fdt_del_node_and_alias(blob, "spi1");
+ } else
+ fdt_del_node_and_alias(blob, "serial3");
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ /* remove dts sdhc node */
+ fdt_del_node_compat(blob, "fsl,esdhc");
+ } else if (romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* remove dts sim node */
+ fdt_del_node_compat(blob, "fsl,sim-v1.0");
+ printf("SIM & SDHC can't work together on the board");
+ printf("\nRemove sim from hwconfig and reset\n");
+ }
+ }
+}
+#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
new file mode 100644
index 0000000..946ad19
--- /dev/null
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {1060, 1333, &ddr_cfg_regs_1333},
+ {0, 0, NULL}
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1870,
+ .caslat_X = 0x1e << 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 15000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 160000,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
new file mode 100644
index 0000000..dc23658
--- /dev/null
+++ b/board/freescale/bsc9132qds/law.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
+#endif
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
new file mode 100644
index 0000000..0e4545f
--- /dev/null
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR (PA) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64K, 1),
+#endif
+
+ /* *I*G - Board FPGA */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index c92902a..2b74d02 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,8 +14,23 @@
#include <common.h>
#include <command.h>
#include <asm/io.h>
+#include <linux/time.h>
+#include <i2c.h>
#include "qixis.h"
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg)
+{
+ return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+}
+
+void qixis_write_i2c(unsigned int reg, u8 value)
+{
+ u8 val = value;
+ i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+}
+#endif
+
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
@@ -30,6 +45,72 @@ void qixis_write(unsigned int reg, u8 value)
out_8(p + reg, value);
}
+u16 qixis_read_minor(void)
+{
+ u16 minor;
+
+ /* this data is in little endian */
+ QIXIS_WRITE(tagdata, 5);
+ minor = QIXIS_READ(tagdata);
+ QIXIS_WRITE(tagdata, 6);
+ minor += QIXIS_READ(tagdata) << 8;
+
+ return minor;
+}
+
+char *qixis_read_time(char *result)
+{
+ time_t time = 0;
+ int i;
+
+ /* timestamp is in 32-bit big endian */
+ for (i = 8; i <= 11; i++) {
+ QIXIS_WRITE(tagdata, i);
+ time = (time << 8) + QIXIS_READ(tagdata);
+ }
+
+ return ctime_r(&time, result);
+}
+
+char *qixis_read_tag(char *buf)
+{
+ int i;
+ char tag, *ptr = buf;
+
+ for (i = 16; i <= 63; i++) {
+ QIXIS_WRITE(tagdata, i);
+ tag = QIXIS_READ(tagdata);
+ *(ptr++) = tag;
+ if (!tag)
+ break;
+ }
+ if (i > 63)
+ *ptr = '\0';
+
+ return buf;
+}
+
+/*
+ * return the string of binary of u8 in the format of
+ * 1010 10_0. The masked bit is filled as underscore.
+ */
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
+{
+ char *ptr;
+ int i;
+
+ ptr = buf;
+ for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+ *(ptr++) = ' ';
+ for (i = 0x08; i > 0 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+
+ *ptr = '\0';
+
+ return buf;
+}
+
void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
@@ -61,7 +142,6 @@ void set_altbank(void)
QIXIS_WRITE(brdcfg[0], reg);
}
-#ifdef DEBUG
static void qixis_dump_regs(void)
{
int i;
@@ -91,7 +171,14 @@ static void qixis_dump_regs(void)
printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
}
-#endif
+
+static void __qixis_dump_switch(void)
+{
+ puts("Reverse engineering switch is not implemented for this board\n");
+}
+
+void qixis_dump_switch(void)
+ __attribute__((weak, alias("__qixis_dump_switch")));
int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -122,16 +209,13 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
}
- }
-
-#ifdef DEBUG
- else if (strcmp(argv[1], "dump") == 0) {
+ } else if (strcmp(argv[1], "dump") == 0) {
qixis_dump_regs();
return 0;
- }
-#endif
-
- else {
+ } else if (strcmp(argv[1], "switch") == 0) {
+ qixis_dump_switch();
+ return 0;
+ } else {
printf("Invalid option: %s\n", argv[1]);
return 1;
}
@@ -146,7 +230,6 @@ U_BOOT_CMD(
"qixis_reset altbank - reset to alternate bank\n"
"qixis watchdog <watchdog_period> - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
-#ifdef DEBUG
"qixis_reset dump - display the QIXIS registers\n"
-#endif
+ "qixis_reset switch - display switch\n"
);
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index b98b180..8d914d5 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -88,8 +88,21 @@ struct qixis {
u8 qixis_read(unsigned int reg);
void qixis_write(unsigned int reg, u8 value);
+u16 qixis_read_minor(void);
+char *qixis_read_time(char *result);
+char *qixis_read_tag(char *buf);
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg);
+void qixis_write_i2c(unsigned int reg, u8 value);
+#endif
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE_I2C(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#endif
#endif
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 21428e3..48f7155 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
new file mode 100644
index 0000000..8df19dd
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 58000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 1071803..648f0ec 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -31,7 +31,7 @@
#include <vsc7385.h>
#include <ns16550.h>
#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
#include <asm/gpio.h>
#endif
@@ -45,7 +45,7 @@ int board_early_init_f(void)
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_f();
#endif
@@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_r();
#endif
@@ -67,7 +67,7 @@ int checkboard(void)
return 0;
}
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
static struct pci_region pci_regions[] = {
{
.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
@@ -140,7 +140,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
}
#endif
-#else /* CONFIG_NAND_SPL */
+#else /* CONFIG_SPL_BUILD */
void board_init_f(ulong bootflag)
{
board_early_init_f();
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index 6d00caf..49310bd 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -99,7 +99,7 @@ unsigned long get_sdram_size(void)
struct cpu_type *cpu;
phys_size_t ddr_size;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014)
ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
@@ -144,7 +144,7 @@ phys_size_t fixed_sdram(void)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
if (cpu->soc_ver == SVR_P1014) {
ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
@@ -237,7 +237,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->trwt_override = 1;
popts->trwt = 0;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index dfeb86f..11e2e8a 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -164,7 +164,7 @@ int checkboard(void)
{
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
@@ -178,7 +178,7 @@ int board_eth_init(bd_t *bis)
struct cpu_type *cpu;
int num = 0;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@@ -283,7 +283,7 @@ void ft_board_setup(void *blob, bd_t *bd)
phys_size_t size;
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
ft_cpu_setup(blob, bd);
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 916439c..b16b8c8 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -202,7 +202,7 @@ phys_size_t fixed_sdram (void)
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 437eaf0..9c6683d 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -108,7 +108,7 @@ int checkboard (void)
else
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
setbits_be32(&pgpio->gpdir, GPIO_DIR);
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index fec9777..4b0d577 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,11 +136,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
}
#endif /* #ifdef CONFIG_FMAN_ENET */
-#define CPLD_LANE_A_SEL 0x1
-#define CPLD_LANE_G_SEL 0x2
-#define CPLD_LANE_C_SEL 0x4
-#define CPLD_LANE_D_SEL 0x8
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -148,10 +143,6 @@ int board_eth_init(bd_t *bis)
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
- u8 mux = CPLD_READ(serdes_mux);
printf("Initializing Fman\n");
@@ -181,36 +172,6 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
- switch (srds_prtcl) {
- case 0x2:
- case 0xf:
- mux &= ~CPLD_LANE_G_SEL;
- break;
- case 0x5:
- case 0x9:
- case 0xa:
- case 0x17:
- mux |= CPLD_LANE_G_SEL;
- break;
- case 0x14:
- mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
- break;
- case 0x8:
- case 0x16:
- case 0x19:
- case 0x1a:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x1c:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
- break;
- default:
- printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
- break;
- }
- CPLD_WRITE(serdes_mux, mux);
-
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index d2732f5..a706a6d 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -43,7 +43,7 @@ DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
@@ -101,6 +101,49 @@ int board_early_init_f(void)
return 0;
}
+#define CPLD_LANE_A_SEL 0x1
+#define CPLD_LANE_G_SEL 0x2
+#define CPLD_LANE_C_SEL 0x4
+#define CPLD_LANE_D_SEL 0x8
+
+void board_config_lanes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ u8 mux = 0;
+ switch (srds_prtcl) {
+ case 0x2:
+ case 0x5:
+ case 0x9:
+ case 0xa:
+ case 0xf:
+ break;
+ case 0x8:
+ mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x14:
+ mux |= CPLD_LANE_A_SEL;
+ break;
+ case 0x17:
+ mux |= CPLD_LANE_G_SEL;
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1a:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x1c:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+ break;
+ default:
+ printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+ break;
+ }
+ CPLD_WRITE(serdes_mux, mux);
+}
+
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -124,6 +167,7 @@ int board_early_init_r(void)
set_liodns();
setup_portals();
+ board_config_lanes_mux();
return 0;
}
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 5debcf6..6f2c5c8 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -40,7 +40,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 88b8ced..3c95f3f 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -42,16 +42,29 @@
DECLARE_GLOBAL_DATA_PTR;
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+ {8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+ {10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+ {10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+ {8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
int checkboard(void)
{
+ char buf[64];
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
@@ -65,6 +78,12 @@ int checkboard(void)
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
@@ -393,3 +412,63 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
}
+
+/*
+ * Reverse engineering switch settings.
+ * Some bits cannot be figured out. They will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[9];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = dutcfg[0];
+ sw[1] = (dutcfg[1] << 0x07) | \
+ ((dutcfg[12] & 0xC0) >> 1) | \
+ ((dutcfg[11] & 0xE0) >> 3) | \
+ ((dutcfg[6] & 0x80) >> 6) | \
+ ((dutcfg[1] & 0x80) >> 7);
+ sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
+ ((brdcfg[1] & 0x30) >> 2) | \
+ ((brdcfg[1] & 0x40) >> 5) | \
+ ((brdcfg[1] & 0x80) >> 7);
+ sw[3] = brdcfg[2];
+ sw[4] = ((dutcfg[2] & 0x01) << 7) | \
+ ((dutcfg[2] & 0x06) << 4) | \
+ ((~QIXIS_READ(present)) & 0x10) | \
+ ((brdcfg[3] & 0x80) >> 4) | \
+ ((brdcfg[3] & 0x01) << 2) | \
+ ((brdcfg[6] == 0x62) ? 3 : \
+ ((brdcfg[6] == 0x5a) ? 2 : \
+ ((brdcfg[6] == 0x5e) ? 1 : 0)));
+ sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
+ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
+ ((brdcfg[0] & 0x40) >> 5);
+ sw[6] = (brdcfg[11] & 0x20);
+ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
+ ((brdcfg[5] & 0x10) << 2);
+ sw[8] = ((brdcfg[12] & 0x08) << 4) | \
+ ((brdcfg[12] & 0x03) << 5);
+
+ puts("DIP switch (reverse-engineering)\n");
+ for (i = 0; i < 9; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h
index c6a3492..f290f3c 100644
--- a/board/freescale/t4qds/t4qds.h
+++ b/board/freescale/t4qds/t4qds.h
@@ -23,15 +23,4 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
- {8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
- {10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
- {10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
- {8, 9}, {9, 8}, {14, 1}, {15, 0} };
#endif
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 078a6e4..80eb511 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -125,7 +125,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_1M, 1),
+ 0, 16, BOOKE_PAGESZ_64K, 1),
#endif
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,