ENGR00132617 MX53: add NAND support

Add NAND support for MX53 EVK and ARD.

Need to use kobs-ng to flash U-Boot on MX53 TO1. Because
MX51 TO1 ROM doesn't support bi swap solution and kernel
enable bi swap, Must enable "ignore bad block" option when
flashing U-Boot. The step is as following:
echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin
echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad

Since default configuration stores environment into SD
card and U-Boot uses get_mmc_env_devno (Read SBMR register)
to get MMC/SD slot information, you must insert SD card to
bottom SD slot to get/store environment if you are using NAND
boot on MX53 EVK.

You must config boot dip setting well when doing NAND boot.
For example, if you are using NAND 29F32G080AA NAND chip on
MX53 EVK, you can set boot dips as the following for NAND
boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on.
Other dips are off.

Signed-off-by: Lily Zhang <r58066@freescale.com>

1 files changed, 182 insertions, 0 deletions

diff --git a/board/freescale/mx53_rd/mx53_rd.c b/board/freescale/mx53_rd/mx53_rd.c
index a4760b0..d88cb38 100644
--- a/board/freescale/mx53_rd/mx53_rd.c
+++ b/board/freescale/mx53_rd/mx53_rd.c
@@ -1021,6 +1021,183 @@ int board_mmc_init(bd_t *bis)
 
 #endif
 
+#ifdef CONFIG_MXC_NAND
+void setup_nfc(void)
+{
+	u32 i, reg;
+	#define M4IF_GENP_WEIM_MM_MASK          0x00000001
+	#define WEIM_GCR2_MUX16_BYP_GRANT_MASK  0x00001000
+
+	reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+	reg &= ~M4IF_GENP_WEIM_MM_MASK;
+	__raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+	for (i = 0x4; i < 0x94; i += 0x18) {
+		reg = __raw_readl(WEIM_BASE_ADDR + i);
+		reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+		__raw_writel(reg, WEIM_BASE_ADDR + i);
+	}
+#if defined(CONFIG_MX53_ARD)
+	mxc_request_iomux(MX53_PIN_NANDF_CS0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS0,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_CS1,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS1,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_RB0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_RB0,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+			PAD_CTL_100K_PU);
+	mxc_request_iomux(MX53_PIN_NANDF_CLE,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CLE,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_ALE,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_ALE,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_WP_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+			PAD_CTL_100K_PU);
+	mxc_request_iomux(MX53_PIN_NANDF_RE_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_WE_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA0,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA1,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA1,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA2,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA2,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA3,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA3,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA4,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA4,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA5,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA5,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA6,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA6,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA7,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA7,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+#else
+	mxc_request_iomux(MX53_PIN_NANDF_CS0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS0,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_CS1,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS1,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_CS2,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS2,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_CS3,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CS3,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_RB0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_RB0,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+			PAD_CTL_100K_PU);
+	mxc_request_iomux(MX53_PIN_NANDF_CLE,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_CLE,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_ALE,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_ALE,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_WP_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+			PAD_CTL_100K_PU);
+	mxc_request_iomux(MX53_PIN_NANDF_RE_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_NANDF_WE_B,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B,
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA0,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA0,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA1,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA1,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA2,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA2,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA3,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA3,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA4,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA4,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA5,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA5,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA6,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA6,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+	mxc_request_iomux(MX53_PIN_EIM_DA7,
+			IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX53_PIN_EIM_DA7,
+			PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
+			PAD_CTL_DRV_HIGH);
+#endif
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_MFG
@@ -1045,6 +1222,11 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
 	setup_uart();
+
+#ifdef CONFIG_MXC_NAND
+	setup_nfc();
+#endif
+
 #ifdef CONFIG_MXC_FEC
 	setup_fec();
 #endif