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| author | Terry Lv <r65388@freescale.com> | 2010-11-17 15:37:49 +0800 |
|---|---|---|
| committer | Terry <r65388@freescale.com> | 2010-12-14 17:20:40 +0800 |
| commit | dca35697e3758ac81894ca305c3f206ff552b697 (patch) | |
| tree | 02cd77b87c58ea0b0a97d9964a1f869b32e0987f /board/freescale | |
| parent | bb24c00fe03c58f9695b0f68e51f35c6c5982746 (diff) | |
| download | u-boot-imx-dca35697e3758ac81894ca305c3f206ff552b697.zip u-boot-imx-dca35697e3758ac81894ca305c3f206ff552b697.tar.gz u-boot-imx-dca35697e3758ac81894ca305c3f206ff552b697.tar.bz2 | |
ENGR00133727: uart outputs messy code when kernel starts on mx51
uart outputs messy code when kernel starts on mx51.
Change uart clock to use pll2 as source clock.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx51_bbg/lowlevel_init.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mx51_bbg/lowlevel_init.S b/board/freescale/mx51_bbg/lowlevel_init.S index 8b9d338..f7f780a 100644 --- a/board/freescale/mx51_bbg/lowlevel_init.S +++ b/board/freescale/mx51_bbg/lowlevel_init.S @@ -242,10 +242,10 @@ str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] - /* Use default for UART clock */ - ldr r1, =0xA6A2A020 + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] - ldr r1, =0x00C30318 + ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] /* make sure divider effective */ |