diff options
| author | Alison Wang <b18965@freescale.com> | 2014-12-09 17:38:14 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:40:24 -0800 |
| commit | 8ab967b6c6007adbd30e58dfa9ef69154a351484 (patch) | |
| tree | 39d70fcc249733fe301bc156e06d29e55690ca60 /board/freescale | |
| parent | d612f0ab34b27be4ad50b1236fbd6c84450997f1 (diff) | |
| download | u-boot-imx-8ab967b6c6007adbd30e58dfa9ef69154a351484.zip u-boot-imx-8ab967b6c6007adbd30e58dfa9ef69154a351484.tar.gz u-boot-imx-8ab967b6c6007adbd30e58dfa9ef69154a351484.tar.bz2 | |
arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/ls1021aqds/MAINTAINERS | 1 | ||||
| -rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 16 | ||||
| -rw-r--r-- | board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 |
3 files changed, 24 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 7a704cf..638833d 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -8,3 +8,4 @@ F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_sdcard_defconfig F: configs/ls1021aqds_qspi_defconfig +F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 9fcd129..691e828 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -187,6 +187,22 @@ void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; +#ifdef CONFIG_NAND_BOOT + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 porsr1, pinctl; + + /* + * There is LS1 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | + DCFG_CCSR_PORSR1_RCW_SRC_I2C); + out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + pinctl); +#endif + /* Set global data pointer */ gd = &gdata; diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg new file mode 100644 index 0000000..222c71d --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0608000a 00000000 00000000 00000000 +60000000 00407900 e0106a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 |