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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2009-02-19 18:20:52 +0300 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-02-23 15:52:35 -0600 |
| commit | 7e91558032a0c1932dd7f4f562f9c7cc55efc496 (patch) | |
| tree | ba1a0a72c0c628bd7759789cd887fd8dbbe840d8 /board/freescale | |
| parent | 50a4d08e8f31debbd4ea12caf1265f3643c38d5b (diff) | |
| download | u-boot-imx-7e91558032a0c1932dd7f4f562f9c7cc55efc496.zip u-boot-imx-7e91558032a0c1932dd7f4f562f9c7cc55efc496.tar.gz u-boot-imx-7e91558032a0c1932dd7f4f562f9c7cc55efc496.tar.bz2 | |
mpc83xx: MPC837XERDB: Add PCIe support
On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe
slots. Let's support them.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mpc837xerdb/pci.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 8bb31fc..83e89cf 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -13,6 +13,7 @@ #include <common.h> #include <mpc83xx.h> #include <pci.h> +#include <asm/io.h> #if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { @@ -36,12 +37,46 @@ static struct pci_region pci_regions[] = { } }; +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + u32 spridr = in_be32(&immr->sysconf.spridr); /* Enable all 5 PCI_CLK_OUTPUTS */ clk->occr |= 0xf8000000; @@ -55,5 +90,27 @@ void pci_init_board(void) pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; mpc83xx_pci_init(1, reg, 0); + + /* There is no PEX in MPC8379 parts. */ + if (PARTID_NO_E(spridr) == SPR_8379) + return; + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg, 0); } #endif /* CONFIG_PCI */ |