ENGR00173966-3: ARM2: i.mx6dl: add the DDR script

integrate DDR script http://compass.freescale.net/livelink/
livelink/225147268/rigel_temp.inc.txt?func=doc.Fetch
&nodeid=225147268

Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>

1 files changed, 133 insertions, 3 deletions

diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S
index a1836e8..d593541 100644
--- a/board/freescale/mx6q_arm2/flash_header.S
+++ b/board/freescale/mx6q_arm2/flash_header.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -56,7 +56,138 @@ boot_data:        .word TEXT_BASE
 image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
 plugin:           .word 0x0
 
-#ifdef CONFIG_LPDDR2
+#if defined CONFIG_MX6DL
+dcd_hdr:          .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */
+
+# IOMUXC_BASE_ADDR  = 0x20e0000
+# DDR IO TYPE
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000c0000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+# Clock
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
+# Address
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+# Control
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+# Data Strobe
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
+# DATA
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030)
+
+# MMDC_P0_BASE_ADDR = 0x021b0000
+# MMDC_P1_BASE_ADDR = 0x021b4000
+# Calibrations
+# ZQ
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+# write leveling
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x00370037)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x00370037)
+# DQS gating, read delay, write delay calibration values
+# based on calibration compare of 0x00ffff00
+MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x41770170)
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x020c016d)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x41770170)
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x02150202)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x47494b49)
+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x48484c47)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x39382b2f)
+MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x2f35312c)
+# read data bit delay
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+# Complete calibration by forced measurment
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+# MMDC init:
+# in DDR3, 64-bit mode, only MMDC0 is initiated:
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2)
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x005b0e21)
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000)
+
+# Initialize 2GB DDR3 - Micron MT41J128M
+# MR2
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803a)
+# MR3
+MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b)
+# MR1
+MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+# MR0
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+# ZQ calibration
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+# final DDR setup
+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x004, 0x00011006)
+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+
+/* enable AXI cache for VDOA/VPU/IPU */
+MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
+MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
+
+#elif defined(CONFIG_LPDDR2)
 dcd_hdr:          .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */
 
@@ -494,7 +625,6 @@ MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x007f007f)
 MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f)
 #endif
 
-
 #else
 
 /*****************PLUGIN IN mode********************/