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| author | Lily Zhang <r58066@freescale.com> | 2012-03-26 19:03:23 +0800 |
|---|---|---|
| committer | Lily Zhang <r58066@freescale.com> | 2012-03-26 19:06:27 +0800 |
| commit | a1db4fa037493e5e6aeeba384e5fe261d0f93c31 (patch) | |
| tree | 471f67a92cd5968e6d94455fea97d82cdeda2a8a /board/freescale | |
| parent | c51f28d353506c754059fe762f258e1749d8166a (diff) | |
| download | u-boot-imx-a1db4fa037493e5e6aeeba384e5fe261d0f93c31.zip u-boot-imx-a1db4fa037493e5e6aeeba384e5fe261d0f93c31.tar.gz u-boot-imx-a1db4fa037493e5e6aeeba384e5fe261d0f93c31.tar.bz2 | |
ENGR00177954 mx6solo sabreauto: remove MMDC1 settingrel_imx_3.0.15_12.03.00
Remove MMDC1 setting from DDR script of mx6solo sabreauto
if it's not used.
Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 83 |
1 files changed, 39 insertions, 44 deletions
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S index 32183a9..8ee4c4a 100644 --- a/board/freescale/mx6q_sabreauto/flash_header.S +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -54,8 +54,8 @@ image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 #if defined CONFIG_MX6SOLO_DDR3 -dcd_hdr: .word 0x408802D2 /* Tag=0xD2, Len=80*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x048402CC /* Tag=0xCC, Len=80*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x406802D2 /* Tag=0xD2, Len=76*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x046402CC /* Tag=0xCC, Len=76*8 + 4, Param=0x04 */ /* DCD */ /* DDR3 initialization based on the MX6Solo Auto Reference Design (ARD) */ @@ -115,51 +115,46 @@ MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) -MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333) -MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333) -MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333) -MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333) - -MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740) - -MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) -MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975) -MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64) -MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB) -MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2) - -MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21) -MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040) -MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036) -MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027) -MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x84190000) - -MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032) -MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) -MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031) -MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030) - -MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) -MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003) -MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) -MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x818, 0x00022227) - -MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x83c, 0x42120212) -MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x840, 0x01790179) -MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x848, 0x42434846) -MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x850, 0x413F2C2E) -MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x80c, 0x001F0001) -MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x810, 0x00010001) -MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) -MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) -MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x004, 0x00025576) -MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) +MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x018, 0x00001740) + +MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) +MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7975) +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64) +MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB) +MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2) + +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x030, 0x008F0E21) +MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x008, 0x09444040) +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x004, 0x00020036) +MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x040, 0x00000027) +MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x000, 0x84190000) + +MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032) +MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031) +MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030) + +MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003) +MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x818, 0x00022227) + +MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x83c, 0x42120212) +MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x840, 0x01790179) +MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x848, 0x42434846) +MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x850, 0x413F2C2E) +MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x80c, 0x001F0001) +MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x810, 0x00010001) +MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) +MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x004, 0x00025576) +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) /* enable AXI cache for VDOA/VPU/IPU */ -MXC_DCD_ITEM(78, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) +MXC_DCD_ITEM(74, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) /* set IPU Qos=0x7 */ -MXC_DCD_ITEM(79, IOMUXC_BASE_ADDR + 0x018, 0x00070007) -MXC_DCD_ITEM(80, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) +MXC_DCD_ITEM(75, IOMUXC_BASE_ADDR + 0x018, 0x00070007) +MXC_DCD_ITEM(76, IOMUXC_BASE_ADDR + 0x01c, 0x00070007) #elif defined CONFIG_LPDDR2 dcd_hdr: .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */ |