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author | Anson Huang <b20788@freescale.com> | 2011-08-22 15:32:10 +0800 |
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committer | Anson Huang <b20788@freescale.com> | 2011-08-22 15:33:56 +0800 |
commit | 4379503e39f059fed62c1f5041e9b99ecb7dd354 (patch) | |
tree | ff1fd30837c31e03cb1fc6fc292bce2ddef4e45a /board/freescale | |
parent | 10ddb7764160b44205152cb52f95986736367f01 (diff) | |
download | u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.zip u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.tar.gz u-boot-imx-4379503e39f059fed62c1f5041e9b99ecb7dd354.tar.bz2 |
ENGR00155156 [MX6]Clean up debug info in uboot
1. ENET don't need to enable ENET pll clock;
2. Enable cpu debug clock in case of using JTAG;
3. Clean up some debug info during bring up.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/mx6q_sabreauto/lowlevel_init.S | 2 | ||||
-rw-r--r-- | board/freescale/mx6q_sabreauto/mx6q_sabreauto.c | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/board/freescale/mx6q_sabreauto/lowlevel_init.S b/board/freescale/mx6q_sabreauto/lowlevel_init.S index a12a61a..fed880a 100644 --- a/board/freescale/mx6q_sabreauto/lowlevel_init.S +++ b/board/freescale/mx6q_sabreauto/lowlevel_init.S @@ -71,7 +71,7 @@ /* Restore the default values in the Gate registers */ ldr r0, CCM_BASE_ADDR_W - ldr r1, =0x3F + ldr r1, =0xC0003F str r1, [r0, #CLKCTL_CCGR0] ldr r1, =0x30FC00 str r1, [r0, #CLKCTL_CCGR1] diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c index 60820a9..95e2fbc 100644 --- a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c +++ b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c @@ -341,7 +341,6 @@ int board_init(void) int board_late_init(void) { - printf("board_late_init\n"); return 0; } |