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authorAllen Xu <allen.xu@freescale.com>2011-11-03 11:15:48 +0800
committerAllen Xu <allen.xu@freescale.com>2011-11-03 11:29:26 +0800
commit13b7fad6b3fc8034738543f5946378239aae440f (patch)
tree12e3d8a4c7462ac6d38c22cb9261c512b748b2bc /board/freescale
parent01a080fe6c11de531f79d0a05d7a06dac1708e41 (diff)
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ENGR00161254 MX6Q: Add NAND support in Uboot
Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mx6q_arm2/mx6q_arm2.c56
1 files changed, 56 insertions, 0 deletions
diff --git a/board/freescale/mx6q_arm2/mx6q_arm2.c b/board/freescale/mx6q_arm2/mx6q_arm2.c
index b7853ac..d48601e 100644
--- a/board/freescale/mx6q_arm2/mx6q_arm2.c
+++ b/board/freescale/mx6q_arm2/mx6q_arm2.c
@@ -404,6 +404,59 @@ void spi_io_init(struct imx_spi_dev_t *dev)
}
#endif
+#ifdef CONFIG_NAND_GPMI
+
+iomux_v3_cfg_t nfc_pads[] = {
+ MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
+ MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
+ MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
+ MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
+ MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
+ MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
+ MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N,
+ MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
+ MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
+ MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
+ MX6Q_PAD_NANDF_D0__RAWNAND_D0,
+ MX6Q_PAD_NANDF_D1__RAWNAND_D1,
+ MX6Q_PAD_NANDF_D2__RAWNAND_D2,
+ MX6Q_PAD_NANDF_D3__RAWNAND_D3,
+ MX6Q_PAD_NANDF_D4__RAWNAND_D4,
+ MX6Q_PAD_NANDF_D5__RAWNAND_D5,
+ MX6Q_PAD_NANDF_D6__RAWNAND_D6,
+ MX6Q_PAD_NANDF_D7__RAWNAND_D7,
+ MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
+};
+
+int setup_gpmi_nand(void)
+{
+ unsigned int reg;
+
+ /* config gpmi nand iomux */
+ mxc_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+
+ /* config gpmi and bch clock to 11Mhz*/
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+ reg &= 0xF800FFFF;
+ reg |= 0x01E40000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ /* enable gpmi and bch clock gating */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR4);
+ reg |= 0xFF003000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR4);
+
+ /* enable apbh clock gating */
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR0);
+ reg |= 0x0030;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR0);
+
+}
+#endif
+
+
#define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
#ifdef CONFIG_MXC_FEC
@@ -706,6 +759,9 @@ int board_init(void)
#endif
#endif
+#ifdef CONFIG_NAND_GPMI
+ setup_gpmi_nand();
+#endif
return 0;
}