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| author | Terry Lv <r65388@freescale.com> | 2010-01-06 15:57:26 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2010-01-06 15:57:26 +0800 |
| commit | c3b0a8706e5b3eb84875830e9acaa80cac088c14 (patch) | |
| tree | eeaea12ab02b93e65e4440700192f322e5073107 /board/freescale | |
| parent | cb4d53ad84e809a9d6d4354db0e140803cff27a2 (diff) | |
| download | u-boot-imx-c3b0a8706e5b3eb84875830e9acaa80cac088c14.zip u-boot-imx-c3b0a8706e5b3eb84875830e9acaa80cac088c14.tar.gz u-boot-imx-c3b0a8706e5b3eb84875830e9acaa80cac088c14.tar.bz2 | |
ENGR00119834: Change PDR0 clock settings for mx35 TO2
The IPU_HND_BYP bit is different in mx35 to1 and to2.
Change the value of this bit for mx35 to2.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx35_3stack/lowlevel_init.S | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/board/freescale/mx35_3stack/lowlevel_init.S b/board/freescale/mx35_3stack/lowlevel_init.S index 9608aa5..e984306 100644 --- a/board/freescale/mx35_3stack/lowlevel_init.S +++ b/board/freescale/mx35_3stack/lowlevel_init.S @@ -216,11 +216,8 @@ ldr r1, =CCM_PPLL_300_HZ str r1, [r0, #CLKCTL_PPCTL] - ldr r1, [r0, #CLKCTL_PDR0] - orr r1, r1, #0x800000 - str r1, [r0, #CLKCTL_PDR0] - ldr r1, =CCM_PDR0_CONFIG + bic r1, r1, #0x800000 str r1, [r0, #CLKCTL_PDR0] ldr r1, [r0, #CLKCTL_CGR0] |