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| author | Stefan Agner <stefan@agner.ch> | 2014-04-23 18:17:51 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-25 15:46:12 +0200 |
| commit | 56d83d1c046c693b65ab09c0e960d922ec639c2b (patch) | |
| tree | 87c48bc6742a97768be857d92f18976665d3feef /board/freescale/vf610twr | |
| parent | 1277bac0d21bfa6952bdb14fcbf4134aa3018056 (diff) | |
| download | u-boot-imx-56d83d1c046c693b65ab09c0e960d922ec639c2b.zip u-boot-imx-56d83d1c046c693b65ab09c0e960d922ec639c2b.tar.gz u-boot-imx-56d83d1c046c693b65ab09c0e960d922ec639c2b.tar.bz2 | |
arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'board/freescale/vf610twr')
| -rw-r--r-- | board/freescale/vf610twr/vf610twr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4ee74c0..d64d3aa 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -217,7 +217,8 @@ void ddr_ctrl_init(void) &ddrmr->cr[139]); writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]); + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]); writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2), &ddrmr->cr[155]); writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); |