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| author | Roy Zang <tie-fei.zang@freescale.com> | 2013-03-25 07:33:15 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:00:25 -0500 |
| commit | 9458f6d83a3b44df1c2ae5c763c4f9fd6e2f9c05 (patch) | |
| tree | 9538eddba53eddde5398ec18d4cbbcf339770094 /board/freescale/t4qds/tlb.c | |
| parent | 3e4c3137d6aefaf45a87bbad701fc336f3f24a3d (diff) | |
| download | u-boot-imx-9458f6d83a3b44df1c2ae5c763c4f9fd6e2f9c05.zip u-boot-imx-9458f6d83a3b44df1c2ae5c763c4f9fd6e2f9c05.tar.gz u-boot-imx-9458f6d83a3b44df1c2ae5c763c4f9fd6e2f9c05.tar.bz2 | |
T4/serdes: fix the serdes clock frequency
Reverse the bit sequence to set and display serdes clock frequency
correctly. The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/tlb.c')
0 files changed, 0 insertions, 0 deletions