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| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2014-04-22 15:10:44 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:53 -0700 |
| commit | b6036993ebf12d360692a7df227537277afe3a1f (patch) | |
| tree | b063445f4cd8225d787bb5a3baa45d36243ada1f /board/freescale/t4qds/tlb.c | |
| parent | cb753850e8af5a224d7c08b4fd1d258082d3bbd5 (diff) | |
| download | u-boot-imx-b6036993ebf12d360692a7df227537277afe3a1f.zip u-boot-imx-b6036993ebf12d360692a7df227537277afe3a1f.tar.gz u-boot-imx-b6036993ebf12d360692a7df227537277afe3a1f.tar.bz2 | |
powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/tlb.c')
| -rw-r--r-- | board/freescale/t4qds/tlb.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b701e75..1e4d096 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -105,6 +105,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -136,6 +137,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |