diff options
| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2014-05-16 10:52:33 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-06-05 12:55:59 -0700 |
| commit | 94752f60eb0d17d30dd1dbc81dac42d9119f5b36 (patch) | |
| tree | 242bcdeb0dfa9ca33baa4eeb7fbe85ec6934ff11 /board/freescale/t4qds/t4_rcw.cfg | |
| parent | 9752eb64260cb51b8c87dcddc73e6270a494e073 (diff) | |
| download | u-boot-imx-94752f60eb0d17d30dd1dbc81dac42d9119f5b36.zip u-boot-imx-94752f60eb0d17d30dd1dbc81dac42d9119f5b36.tar.gz u-boot-imx-94752f60eb0d17d30dd1dbc81dac42d9119f5b36.tar.bz2 | |
powerpc/t4qds: Add alternate serdes protocols to align with A-007186
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.
Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/t4_rcw.cfg')
| -rw-r--r-- | board/freescale/t4qds/t4_rcw.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg index 3e56817..6f09a7b 100644 --- a/board/freescale/t4qds/t4_rcw.cfg +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 010e0100 -#serdes protocol 1_28_6_12 +#serdes protocol 1_27_5_11 16070019 18101916 00000000 00000000 -04383060 30548c00 ec020000 f5000000 +04362858 30548c00 ec020000 f5000000 00000000 ee0000ee 00000000 000307fc 00000000 00000000 00000000 00000028 |