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| author | Tom Rini <trini@ti.com> | 2014-07-28 14:54:29 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-28 14:54:29 -0400 |
| commit | d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca (patch) | |
| tree | 1df8ab92fd228598d5884db37cceddcb18a0c020 /board/freescale/t4qds/t4240qds.c | |
| parent | ee860c60d2c5283c009f7ea740c6ee706da87cb7 (diff) | |
| parent | fb5368789a45ca5ee4396cbbf563a8f16ab24f9c (diff) | |
| download | u-boot-imx-d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca.zip u-boot-imx-d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca.tar.gz u-boot-imx-d5f8a6ddd41dee0de17888f8b5334fe1b636c4ca.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t4qds/t4240qds.c')
| -rw-r--r-- | board/freescale/t4qds/t4240qds.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6205fea 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -528,7 +528,7 @@ int config_backside_crossbar_mux(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -539,8 +539,14 @@ int board_early_init_r(void) flush_dcache(); invalidate_icache(); - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); + if (flash_esel == -1) { + /* very unlikely unless something is messed up */ + puts("Error: Could not find TLB for FLASH BASE\n"); + flash_esel = 2; /* give our best effort to continue */ + } else { + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + } set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -638,9 +644,10 @@ unsigned long get_board_ddr_clk(void) int misc_init_r(void) { u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *srds_regs; u32 actual[MAX_SERDES]; + u32 pllcr0, expected; unsigned int i; sw = QIXIS_READ(brdcfg[2]); @@ -663,8 +670,9 @@ int misc_init_r(void) } for (i = 0; i < MAX_SERDES; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + srds_regs = srds_base + i * 0x1000; + pllcr0 = srds_regs->bank[0].pllcr0; + expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), |