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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-04-18 16:43:40 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:52 -0700 |
| commit | 4d66668300439972abc4990f23fdea771f0830fd (patch) | |
| tree | c76dc30eda02664de93aceaf9332ca05671220ef /board/freescale/t208xrdb/ddr.c | |
| parent | b19e288f47ea7db98eefbebdda0fe0fad66d845c (diff) | |
| download | u-boot-imx-4d66668300439972abc4990f23fdea771f0830fd.zip u-boot-imx-4d66668300439972abc4990f23fdea771f0830fd.tar.gz u-boot-imx-4d66668300439972abc4990f23fdea771f0830fd.tar.bz2 | |
board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xrdb/ddr.c')
| -rw-r--r-- | board/freescale/t208xrdb/ddr.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 01e9173..8a26276 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -100,13 +100,15 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } |