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| author | Stefano Babic <sbabic@denx.de> | 2014-04-04 11:35:30 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-04-04 11:35:30 +0200 |
| commit | 1cad23c5f471d695bed1e3907e30caee3c2a3056 (patch) | |
| tree | 34e035df5db9b327aeae36eff9d0645a915e3177 /board/freescale/t208xrdb/cpld.h | |
| parent | 5dd73bc0a40a4b318195eab871a1f535aad6b43b (diff) | |
| parent | 00b132bf34c5be86a108ac7fe8231ad9e97f6de4 (diff) | |
| download | u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.zip u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.tar.gz u-boot-imx-1cad23c5f471d695bed1e3907e30caee3c2a3056.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm into master
Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale/t208xrdb/cpld.h')
| -rw-r--r-- | board/freescale/t208xrdb/cpld.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h new file mode 100644 index 0000000..4cee4e5 --- /dev/null +++ b/board/freescale/t208xrdb/cpld.h @@ -0,0 +1,42 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CPLD register set of T2080RDB board-specific. + */ +struct cpld_data { + u8 chip_id1; /* 0x00 - Chip ID1 register */ + u8 chip_id2; /* 0x01 - Chip ID2 register */ + u8 hw_ver; /* 0x02 - Hardware Revision Register */ + u8 sw_ver; /* 0x03 - Software Revision register */ + u8 res0[12]; /* 0x04 - 0x0F - not used */ + u8 reset_ctl; /* 0x10 - Reset control Register */ + u8 flash_csr; /* 0x11 - Flash control and status register */ + u8 thermal_csr; /* 0x12 - Thermal control and status register */ + u8 led_csr; /* 0x13 - LED control and status register */ + u8 sfp_csr; /* 0x14 - SFP+ control and status register */ + u8 misc_csr; /* 0x15 - Misc control and status register */ + u8 boot_or; /* 0x16 - Boot config override register */ + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */ + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */ +} cpld_data_t; + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) \ + cpld_write(offsetof(struct cpld_data, reg), value) + +/* CPLD on IFC */ +#define CPLD_LBMAP_MASK 0x3F +#define CPLD_BANK_SEL_MASK 0x07 +#define CPLD_BANK_OVERRIDE 0x40 +#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ +#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ +#define CPLD_LBMAP_RESET 0xFF +#define CPLD_LBMAP_SHIFT 0x03 +#define CPLD_BOOT_SEL 0x80 |