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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2014-04-18 16:43:39 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:52 -0700 |
| commit | b19e288f47ea7db98eefbebdda0fe0fad66d845c (patch) | |
| tree | 1154266ccb7c320ae5be58f55b34f4eba651167c /board/freescale/t208xqds/tlb.c | |
| parent | d1c561cd546353686b28199bf9a90810805c7ada (diff) | |
| download | u-boot-imx-b19e288f47ea7db98eefbebdda0fe0fad66d845c.zip u-boot-imx-b19e288f47ea7db98eefbebdda0fe0fad66d845c.tar.gz u-boot-imx-b19e288f47ea7db98eefbebdda0fe0fad66d845c.tar.bz2 | |
board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t208xqds/tlb.c')
| -rw-r--r-- | board/freescale/t208xqds/tlb.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 62cd110..8d60298 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -65,6 +65,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -110,6 +111,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -141,6 +143,11 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 19, BOOKE_PAGESZ_2G, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |