powerpc/t2081qds: Add T2081 QDS board support

T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.

T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
  prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
  - Two on-board 10M/100M/1G bps RGMII ports
  - Two 10Gbps XFI with on-board SFP+ cage
  - 1Gbps/2.5Gbps SGMII Riser card
  - 10Gbps XAUI Riser card
- Accelerator:
  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
  - 8 lanes up to 10.3125GHz
  - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
  - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
  - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
  - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
  - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
- I2C:
  - Four I2C controllers.
- UART:
  - Dual 4-pins UART serial ports

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1 files changed, 49 insertions, 0 deletions

diff --git a/board/freescale/t208xqds/t208xqds_qixis.h b/board/freescale/t208xqds/t208xqds_qixis.h
new file mode 100644
index 0000000..bdcdc12
--- /dev/null
+++ b/board/freescale/t208xqds/t208xqds_qixis.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __T208xQDS_QIXIS_H__
+#define __T208xQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T208xQDS */
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK             0xE0
+#define BRDCFG4_EMISEL_SHIFT            5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                 0x0
+#define QIXIS_SYSCLK_83                 0x1
+#define QIXIS_SYSCLK_100                0x2
+#define QIXIS_SYSCLK_125                0x3
+#define QIXIS_SYSCLK_133                0x4
+#define QIXIS_SYSCLK_150                0x5
+#define QIXIS_SYSCLK_160                0x6
+#define QIXIS_SYSCLK_166                0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                 0x0
+#define QIXIS_DDRCLK_100                0x1
+#define QIXIS_DDRCLK_125                0x2
+#define QIXIS_DDRCLK_133                0x3
+
+#define BRDCFG5_IRE                     0x20    /* i2c Remote i2c1 enable */
+
+#define BRDCFG9_SFP_TX_EN		0x10
+
+#define BRDCFG12_SD3EN_MASK             0x20
+#define BRDCFG12_SD3MX_MASK             0x08
+#define BRDCFG12_SD3MX_SLOT5            0x08
+#define BRDCFG12_SD3MX_SLOT6            0x00
+#define BRDCFG12_SD4EN_MASK             0x04
+#define BRDCFG12_SD4MX_MASK             0x03
+#define BRDCFG12_SD4MX_SLOT7            0x02
+#define BRDCFG12_SD4MX_SLOT8            0x01
+#define BRDCFG12_SD4MX_AURO_SATA        0x00
+#endif