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authorvijay rai <vijay.rai@freescale.com>2015-02-03 13:02:41 +0000
committerYork Sun <yorksun@freescale.com>2015-03-05 12:03:22 -0800
commit2372e283e56c5edc09f1c900c4b806d78a38d177 (patch)
tree5240bfda7d5ea6f5f70cb223573032b3f760ce33 /board/freescale/t104xrdb/ddr.h
parent703f5681675fd818a7cd1e83ac658b57a3e17f16 (diff)
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mpc85xx/t104xrdb : remove raw timing parameter
This board uses DDR DIMM. Reading SPD provides more flexibility. Raw timing parameter code should be removed after debugging. Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t104xrdb/ddr.h')
-rw-r--r--board/freescale/t104xrdb/ddr.h29
1 files changed, 0 insertions, 29 deletions
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index 09b30b9..ab1c32d 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -6,35 +6,6 @@
#ifndef __DDR_H__
#define __DDR_H__
-dimm_params_t ddr_raw_timing = {
- .n_ranks = 2,
- .rank_density = 2147483648u,
- .capacity = 4294967296u,
- .primary_sdram_width = 64,
- .ec_sdram_width = 8,
- .registered_dimm = 0,
- .mirrored_dimm = 0,
- .n_row_addr = 15,
- .n_col_addr = 10,
- .n_banks_per_sdram_device = 8,
- .edc_config = 2, /* ECC */
- .burst_lengths_bitmask = 0x0c,
- .tckmin_x_ps = 1071,
- .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
- .taa_ps = 13125,
- .twr_ps = 15000,
- .trcd_ps = 13125,
- .trrd_ps = 6000,
- .trp_ps = 13125,
- .tras_ps = 34000,
- .trc_ps = 48125,
- .trfc_ps = 260000,
- .twtr_ps = 7500,
- .trtp_ps = 7500,
- .refresh_rate_ps = 7800000,
- .tfaw_ps = 35000,
-};
-
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;