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| author | Tom Rini <trini@ti.com> | 2014-04-25 14:53:51 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-04-25 14:53:51 -0400 |
| commit | 080d897585428d0fd42c237abfb6746908f4effc (patch) | |
| tree | dc65d6d4bbbf1a7f06bbb045a981270a7624ec67 /board/freescale/t1040qds/ddr.h | |
| parent | adcdeacc3eda1e5949e54062aa99c299e12483be (diff) | |
| parent | 08ad9b068afb8842df4cd559c327f54a42811a8d (diff) | |
| download | u-boot-imx-080d897585428d0fd42c237abfb6746908f4effc.zip u-boot-imx-080d897585428d0fd42c237abfb6746908f4effc.tar.gz u-boot-imx-080d897585428d0fd42c237abfb6746908f4effc.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/t1040qds/ddr.h')
| -rw-r--r-- | board/freescale/t1040qds/ddr.h | 37 |
1 files changed, 19 insertions, 18 deletions
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index afa72af..a6e1673 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,9 +14,6 @@ struct board_specific_parameters { u32 wrlvl_start; u32 wrlvl_ctl_2; u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; }; /* @@ -28,21 +25,25 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807, 0xff, 2, 0}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09, 0xff, 2, 0}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A, 0xff, 2, 0}, +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, +#elif defined(CONFIG_SYS_FSL_DDR3) + {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, +#else +#error DDR type not defined +#endif {} }; |