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| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2013-03-25 07:40:18 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 16:54:13 -0500 |
| commit | f9539a9caa12195870cfc3b0cf6150755aeb2e52 (patch) | |
| tree | 4b62c6605d5067a66a115766add4ff1b571ab298 /board/freescale/p2041rdb | |
| parent | 0fecbba80ad21b1148265c7659f370838069c560 (diff) | |
| download | u-boot-imx-f9539a9caa12195870cfc3b0cf6150755aeb2e52.zip u-boot-imx-f9539a9caa12195870cfc3b0cf6150755aeb2e52.tar.gz u-boot-imx-f9539a9caa12195870cfc3b0cf6150755aeb2e52.tar.bz2 | |
powerpc/p2041: fix serdes reference clock frequency display for PC board
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p2041rdb')
| -rw-r--r-- | board/freescale/p2041rdb/p2041rdb.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index a706a6d..44d3e0c 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -227,6 +227,17 @@ int misc_init_r(void) "'00' is unsupported\n"); else actual[i] = freq[i][clock]; + + /* + * PC board uses a different CPLD with PB board, this CPLD + * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB + * board has cpld_ver_sub = 0, and pcba_ver = 4. + */ + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && + (CPLD_READ(pcba_ver) == 5)) { + /* PC board bank2 frequency */ + actual[i] = freq[i-1][clock]; + } } for (i = 0; i < NUM_SRDS_BANKS; i++) { |