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| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-01-30 11:19:15 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-02-12 13:52:30 +0100 |
| commit | ada02b84636242f5142f74016dbedb50889e93d0 (patch) | |
| tree | 4468b2a516e6337b5fe0fc80ab53a1a3eeb4dcd8 /board/freescale/p2041rdb/eth.c | |
| parent | aa53149e1108ab9395ee8309ce6f90480bfdf34b (diff) | |
| download | u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.zip u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.tar.gz u-boot-imx-ada02b84636242f5142f74016dbedb50889e93d0.tar.bz2 | |
imx: mx6q DDR3 init: Fix SDE_to_RST
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded
as 0x10 for the bit-field MMDC1_MDOR[13:8].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Diffstat (limited to 'board/freescale/p2041rdb/eth.c')
0 files changed, 0 insertions, 0 deletions