Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/p3060: Add SoC related support for P3060 platform
  powerpc/85xx: Add support for setting up RAID engine liodns on P5020
  powerpc/85xx: Refactor some defines out of corenet_ds.h
  fm-eth: Add ability for board code to disable a port
  powerpc/mpc8548: Add workaround for erratum NMG_LBC103
  powerpc/mpc8548: Add workaround for erratum NMG_DDR120
  powerpc/mpc85xxcds: Fix PCI speed
  powerpc/mpc8548cds: Fix booting message
  powerpc/p4080: Add support for secure boot flow
  powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
  powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
  powerpc/p2041rdb: remove watch dog related codes
  powerpc/p2041rdb: updated description of cpld command
  powerpc/p2041rdb: add more ddr frequencies support
  powerpc/p2041rdb: set sysclk according to status of physical switch SW1
  powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
  powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
  powerpc/mpc8xxx: Add DDR2 to unified DDR driver
  powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
  powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
  powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
  powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  powerpc/85xx: Enable CMD_REGINFO on corenet boards
  powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  powerpc/85xx: Fix USB protocol definitions for P1020RDB
  powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
  powerpc/mpc8xxx: Move DDR RCW overriding to common code
  powerpc/mpc8xxx: Extend CWL table
  powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
  powerpc/85xx: Cleanup extern in corenet_ds board code
  powerpc/p2041rdb: Add ethernet support on P2041RDB board
  powerpc/85xx: Add networking support to P1023RDS
  powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
  powerpc/85xx: Add FMan ethernet support to P4080DS
  powerpc/85xx: Add support for FMan ethernet in Independent mode
  powerpc/mpc8548cds: Cleanup mpc8548cds.c
  powerpc/mp: add support for discontiguous cores
  powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
  fdt: Add new fdt_create_phandle helper
  fdt: Rename fdt_create_phandle to fdt_set_phandle
  powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
  fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
  powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
  fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
  powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
  powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
  nand: Freescale Integrated Flash Controller NAND support
  powerpc/85xx: Add basic support for P1010RDB
  powerpc/85xx: Add support for new P102x/P2020 RDB style boards
  powerpc/85xx: relocate CCSR before creating the initial RAM area
  powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
  powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
  powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014

1 files changed, 17 insertions, 26 deletions

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 8e1f46e..a4bcc18 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -53,7 +53,11 @@ void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
  */
 void __cpld_set_altbank(void)
 {
+	u8 reg5 = CPLD_READ(sw_ctl_on);
+
+	CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
 	CPLD_WRITE(fbank_sel, 1);
+	CPLD_WRITE(system_rst, 1);
 }
 void cpld_set_altbank(void)
 	__attribute__((weak, alias("__cpld_set_altbank")));
@@ -61,12 +65,12 @@ void cpld_set_altbank(void)
 /**
  * Set the boot bank to the default bank
  */
-void __cpld_clear_altbank(void)
+void __cpld_set_defbank(void)
 {
-	CPLD_WRITE(fbank_sel, 0);
+	CPLD_WRITE(system_rst_default, 1);
 }
-void cpld_clear_altbank(void)
-	__attribute__((weak, alias("__cpld_clear_altbank")));
+void cpld_set_defbank(void)
+	__attribute__((weak, alias("__cpld_set_defbank")));
 
 #ifdef DEBUG
 static void cpld_dump_regs(void)
@@ -75,7 +79,6 @@ static void cpld_dump_regs(void)
 	printf("cpld_ver_sub	= 0x%02x\n", CPLD_READ(cpld_ver_sub));
 	printf("pcba_ver	= 0x%02x\n", CPLD_READ(pcba_ver));
 	printf("system_rst	= 0x%02x\n", CPLD_READ(system_rst));
-	printf("wd_cfg		= 0x%02x\n", CPLD_READ(wd_cfg));
 	printf("sw_ctl_on	= 0x%02x\n", CPLD_READ(sw_ctl_on));
 	printf("por_cfg		= 0x%02x\n", CPLD_READ(por_cfg));
 	printf("switch_strobe	= 0x%02x\n", CPLD_READ(switch_strobe));
@@ -92,7 +95,6 @@ static void cpld_dump_regs(void)
 int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	int rc = 0;
-	unsigned int i;
 
 	if (argc <= 1)
 		return cmd_usage(cmdtp);
@@ -101,16 +103,7 @@ int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		if (strcmp(argv[2], "altbank") == 0)
 			cpld_set_altbank();
 		else
-			cpld_clear_altbank();
-
-		cpld_reset();
-	} else if (strcmp(argv[1], "watchdog") == 0) {
-		static char *period[8] = {"1ms", "10ms", "30ms", "disable",
-			"100ms", "1s", "10s", "60s"};
-		for (i = 0; i < ARRAY_SIZE(period); i++) {
-			if (strcmp(argv[2], period[i]) == 0)
-				CPLD_WRITE(wd_cfg, i);
-		}
+			cpld_set_defbank();
 	} else if (strcmp(argv[1], "lane_mux") == 0) {
 		u32 lane = simple_strtoul(argv[2], NULL, 16);
 		u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
@@ -154,17 +147,15 @@ U_BOOT_CMD(
 	"Reset the board or pin mulexing selection using the CPLD sequencer",
 	"reset - hard reset to default bank\n"
 	"cpld_cmd reset altbank - reset to alternate bank\n"
-	"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
-	"	period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
 	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
-	"	lane 6: 0 -> slot1 (Default)\n"
-	"		1 -> SGMII\n"
-	"	lane a: 0 -> slot2 (Default)\n"
-	"		1 -> AURORA\n"
-	"	lane c: 0 -> slot2 (Default)\n"
-	"		1 -> SATA0\n"
-	"	lane d: 0 -> slot2 (Default)\n"
-	"		1 -> SATA1\n"
+	"	lane 6: 0 -> slot1\n"
+	"		1 -> SGMII (Default)\n"
+	"	lane a: 0 -> slot2\n"
+	"		1 -> AURORA (Default)\n"
+	"	lane c: 0 -> slot2\n"
+	"		1 -> SATA0 (Default)\n"
+	"	lane d: 0 -> slot2\n"
+	"		1 -> SATA1 (Default)\n"
 #ifdef DEBUG
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif