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| author | Vivek Mahajan <vivek.mahajan@freescale.com> | 2009-10-27 12:18:55 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:33:51 -0500 |
| commit | 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc (patch) | |
| tree | 25395b163b80a1acae7f69b9a515f110d9bdf364 /board/freescale/p2020ds/p2020ds.c | |
| parent | 273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa (diff) | |
| download | u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.zip u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.tar.gz u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.tar.bz2 | |
ppc/85xx/pci: fsl_pci_init: pcie agent mode support
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/p2020ds/p2020ds.c')
| -rw-r--r-- | board/freescale/p2020ds/p2020ds.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e38c014..9878fba 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -227,7 +227,7 @@ void pci_init_board(void) pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); + &pcie2_hose, first_free_busno, pcie_ep); /* * The workaround doesn't work on p2020 because the location @@ -267,7 +267,7 @@ void pci_init_board(void) pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); + &pcie3_hose, first_free_busno, pcie_ep); } else { printf(" PCIE3: disabled\n"); } @@ -286,7 +286,7 @@ void pci_init_board(void) pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); + &pcie1_hose, first_free_busno, pcie_ep); } else { printf(" PCIE1: disabled\n"); } |