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| author | Peter Tyser <ptyser@xes-inc.com> | 2010-01-17 15:38:26 -0600 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-01-17 23:06:44 +0100 |
| commit | 64917ca38933d10b3763f61df7a1e58e1e127b52 (patch) | |
| tree | 1f2b2e4f7160311b5c6c75110e9e6623f5dbf43c /board/freescale/p2020ds/p2020ds.c | |
| parent | 6a45e384955262882375a2785426dc65aeb636c4 (diff) | |
| download | u-boot-imx-64917ca38933d10b3763f61df7a1e58e1e127b52.zip u-boot-imx-64917ca38933d10b3763f61df7a1e58e1e127b52.tar.gz u-boot-imx-64917ca38933d10b3763f61df7a1e58e1e127b52.tar.bz2 | |
PCIe, USB: Replace 'end point' references with 'endpoint'
When referring to PCIe and USB 'endpoint' is the standard naming
convention.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
Diffstat (limited to 'board/freescale/p2020ds/p2020ds.c')
| -rw-r--r-- | board/freescale/p2020ds/p2020ds.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 599caa2..f6eae55 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -222,7 +222,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); @@ -262,7 +262,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); @@ -281,7 +281,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", + pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); |