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| author | Scott Wood <scottwood@freescale.com> | 2012-10-12 18:02:24 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2012-11-26 15:41:27 -0600 |
| commit | 13d1143ffb4dc0c71478534b6b52402e95be9420 (patch) | |
| tree | 0fb8cac0505d385547eb44f4c4afc35165ac7e62 /board/freescale/p1_p2_rdb_pc/ddr.c | |
| parent | d674bccf738396ecdc4374f5b5cb3e7fd376a0ab (diff) | |
| download | u-boot-imx-13d1143ffb4dc0c71478534b6b52402e95be9420.zip u-boot-imx-13d1143ffb4dc0c71478534b6b52402e95be9420.tar.gz u-boot-imx-13d1143ffb4dc0c71478534b6b52402e95be9420.tar.bz2 | |
powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc/ddr.c')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/ddr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 88ba56f..9355536 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#ifdef CONFIG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } +#endif void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, |