Merge branch 'next' of ../next

7 files changed, 784 insertions, 0 deletions

diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile
new file mode 100644
index 0000000..ad1b769
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-$(CONFIG_PCI)  += pci.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk
new file mode 100644
index 0000000..abd64bb
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -0,0 +1,29 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p1_p2rdb board
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
new file mode 100644
index 0000000..9518392
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num);
+
+#define DATARATE_400MHZ 400000000
+#define DATARATE_533MHZ 533333333
+#define DATARATE_667MHZ 666666666
+#define DATARATE_800MHZ 800000000
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_PD_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0x43000000	/* Type = DDR2*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000000
+#define CONFIG_SYS_DDR_TIMING_5		0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_3_400	0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_400	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_400	0x39355322
+#define CONFIG_SYS_DDR_TIMING_2_400	0x1f9048ca
+#define CONFIG_SYS_DDR_CLK_CTRL_400	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_400	0x00480432
+#define CONFIG_SYS_DDR_MODE_2_400	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_400	0x06180100
+
+#define CONFIG_SYS_DDR_TIMING_3_533	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_533	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_533	0x4c47c432
+#define CONFIG_SYS_DDR_TIMING_2_533	0x0f9848ce
+#define CONFIG_SYS_DDR_CLK_CTRL_533	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_533	0x00040642
+#define CONFIG_SYS_DDR_MODE_2_533	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_533	0x08200100
+
+#define CONFIG_SYS_DDR_TIMING_3_667	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
+#define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_667	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_667	0x00040852
+#define CONFIG_SYS_DDR_MODE_2_667	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00040000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b6543
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02000000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00440862
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0a280100
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram (void)
+{
+	sys_info_t sysinfo;
+	char buf[32];
+
+	get_sys_info(&sysinfo);
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, sysinfo.freqDDRBus));
+
+	if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0);
+	else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0);
+	else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0);
+	else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
+		fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0);
+	else
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+					strmhz(buf, sysinfo.freqDDRBus));
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+	dram_size = fixed_sdram();
+	set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c
new file mode 100644
index 0000000..12d2bf4
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/law.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
new file mode 100644
index 0000000..4c03468
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define VSC7385_RST_SET		0x00080000
+#define SLIC_RST_SET		0x00040000
+#define SGMII_PHY_RST_SET	0x00020000
+#define PCIE_RST_SET		0x00010000
+#define RGMII_PHY_RST_SET	0x02000000
+
+#define USB_RST_CLR		0x04000000
+
+#define GPIO_DIR		0x060f0000
+
+#define BOARD_PERI_RST_SET	VSC7385_RST_SET | SLIC_RST_SET | \
+				SGMII_PHY_RST_SET | PCIE_RST_SET | \
+				RGMII_PHY_RST_SET
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+#define BOARDREV_B	0x10100000
+#define BOARDREV_C	0x00100000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_50	50000000
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	u32 val_gpdat, sysclk_gpio, board_rev_gpio;
+
+	val_gpdat = pgpio->gpdat;
+	sysclk_gpio = val_gpdat & SYSCLK_MASK;
+	board_rev_gpio = val_gpdat & BOARDREV_MASK;
+	if (board_rev_gpio == BOARDREV_C) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_100;
+	} else if (board_rev_gpio == BOARDREV_B) {
+		if(sysclk_gpio == 0)
+			return SYSCLK_66;
+		else
+			return SYSCLK_50;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD |
+			 MPC85xx_PMUXCR_SDHC_WP));
+	return 0;
+}
+#endif
+
+int checkboard (void)
+{
+	u32 val_gpdat, board_rev_gpio;
+	volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+	char board_rev = 0;
+	struct cpu_type *cpu;
+
+	val_gpdat = pgpio->gpdat;
+	board_rev_gpio = val_gpdat & BOARDREV_MASK;
+	if (board_rev_gpio == BOARDREV_C)
+		board_rev = 'C';
+	else if (board_rev_gpio == BOARDREV_B)
+		board_rev = 'B';
+	else
+		panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
+
+	cpu = gd->cpu;
+	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
+	setbits_be32(&pgpio->gpdir, GPIO_DIR);
+
+/*
+ * Bringing the following peripherals out of reset via GPIOs
+ * 0 = reset and 1 = out of reset
+ * GPIO12 - Reset to Ethernet Switch
+ * GPIO13 - Reset to SLIC/SLAC devices
+ * GPIO14 - Reset to SGMII_PHY_N
+ * GPIO15 - Reset to PCIe slots
+ * GPIO6  - Reset to RGMII PHY
+ * GPIO5  - Reset to USB3300 devices 1 = reset and 0 = out of reset
+ */
+	clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = 2;
+
+	/*
+	 * Remap Boot flash region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_16M, 1);
+	return 0;
+}
+
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+	char *tmp;
+	unsigned int vscfw_addr;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+#ifdef CONFIG_VSC7385_ENET
+/* If a VSC7385 microcode image is present, then upload it. */
+	if ((tmp = getenv ("vscfw_addr")) != NULL) {
+		vscfw_addr = simple_strtoul (tmp, NULL, 16);
+		printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
+		if (vsc7385_upload_firmware((void *) vscfw_addr,
+					CONFIG_VSC7385_IMAGE_SIZE))
+			puts("Failure uploading VSC7385 microcode.\n");
+	} else
+		puts("No address specified for VSC7385 microcode.\n");
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
new file mode 100644
index 0000000..174a8a7
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+void pci_init_board(void)
+{
+	struct fsl_pci_info pci_info[2];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint devdisr = in_be32(&gur->devdisr);
+	uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+	int num = 0;
+	int first_free_busno = 0;
+
+	int pcie_ep, pcie_configured;
+
+	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+			devdisr, io_sel, host_agent);
+
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		printf ("    eTSEC2 is in sgmii mode.\n");
+
+#ifdef CONFIG_PCIE2
+	SET_STD_PCIE_INFO(pci_info[num], 2);
+	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+		(host_agent == 6) || (host_agent == 0);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		puts ("\n    PCIE2 connected to Slot 1 as ");
+		printf ("%s (base address %lx)",
+			pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie2_hose, first_free_busno);
+		num++;
+	} else {
+		printf ("    PCIE2: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+	SET_STD_PCIE_INFO(pci_info[num], 1);
+
+	pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
+		(host_agent == 5);
+	pcie_configured  = (io_sel == 0xE);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		puts ("\n    PCIE1 connected to Slot 2 as ");
+		printf ("%s (base address %lx)",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num],
+					&pcie1_hose, first_free_busno);
+		num++;
+	} else {
+		printf ("    PCIE1: disabled\n");
+	}
+#else
+	set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+}
+
+void ft_pci_board_setup(void *blob)
+{
+/* According to h/w manual, PCIE2 is at lower address(0x9000)
+ * than PCIE1(0xa000).
+ * Hence PCIE2 is made to occupy the pci1 position in dts to
+ * keep the addresses sorted there.
+ * Generally the case with all FSL SOCs.
+ */
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+}
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
new file mode 100644
index 0000000..cf9bffe
--- /dev/null
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+			0, 2, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_1M, 1),
+
+	/* *I*G - VSC7385 Switch */
+	SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1M, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);