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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 00:06:03 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 00:06:03 +0200 |
commit | e825b100d209a9d3c79b2998452cafa94eec986a (patch) | |
tree | e1654c4d745839eba8d37f67d15acde79382e23e /board/freescale/p1022ds/tlb.c | |
parent | b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c (diff) | |
parent | 66a62ce0dc48d2319938c72f34a562f519c5d5c2 (diff) | |
download | u-boot-imx-e825b100d209a9d3c79b2998452cafa94eec986a.zip u-boot-imx-e825b100d209a9d3c79b2998452cafa94eec986a.tar.gz u-boot-imx-e825b100d209a9d3c79b2998452cafa94eec986a.tar.bz2 |
Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'
Diffstat (limited to 'board/freescale/p1022ds/tlb.c')
-rw-r--r-- | board/freescale/p1022ds/tlb.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 71e71f7..3acc449 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -41,6 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -67,24 +68,31 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SYS_RAMBOOT - /* *I*G - eSDHC/eSPI/NAND boot */ +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) + /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), - - /* map the second 1G */ + /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1G, 1), #endif -# + +#ifdef CONFIG_SYS_NAND_BASE + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), +#endif + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |