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| author | York Sun <yorksun@freescale.com> | 2012-02-29 12:36:51 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-04-24 23:58:30 -0500 |
| commit | 1ba62f10172ead798a8176435cfffff2f79f21c5 (patch) | |
| tree | 5e9b575825060fae4ebefa3193ad5f1124c0fefd /board/freescale/p1010rdb | |
| parent | 119a55f9cff4884a0ad3353d8752ee8787e232da (diff) | |
| download | u-boot-imx-1ba62f10172ead798a8176435cfffff2f79f21c5.zip u-boot-imx-1ba62f10172ead798a8176435cfffff2f79f21c5.tar.gz u-boot-imx-1ba62f10172ead798a8176435cfffff2f79f21c5.tar.bz2 | |
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb')
| -rw-r--r-- | board/freescale/p1010rdb/ddr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index e5d8423..36c8545 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DDR_RAW_TIMING +#ifndef CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DRAM_SIZE 1024 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { @@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } -#else /* CONFIG_DDR_RAW_TIMING */ +#else /* CONFIG_SYS_DDR_RAW_TIMING */ /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } -#endif /* CONFIG_DDR_RAW_TIMING */ +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ |