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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-05-07 11:19:55 +0530 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 17:08:47 -0500 |
| commit | f64bd7c038468de7b6cfa47e88dd0f5ce6c38504 (patch) | |
| tree | 89bb895f51f24167e88ecdb7a96b8f5dbd4df519 /board/freescale/p1010rdb | |
| parent | 8bd00c9494a19ef4ea2a0a9aa695ff111a380850 (diff) | |
| download | u-boot-imx-f64bd7c038468de7b6cfa47e88dd0f5ce6c38504.zip u-boot-imx-f64bd7c038468de7b6cfa47e88dd0f5ce6c38504.tar.gz u-boot-imx-f64bd7c038468de7b6cfa47e88dd0f5ce6c38504.tar.bz2 | |
powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries.
So create new TLB entry only during NAND SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb')
| -rw-r--r-- | board/freescale/p1010rdb/tlb.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 7a8690a..0a8159a 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -43,9 +43,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#ifdef CONFIG_SPL_NAND_MINIMAL SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_8K, 1), + 0, 10, BOOKE_PAGESZ_4K, 1), +#endif /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |