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| author | Ying Zhang <b40530@freescale.com> | 2014-01-24 15:50:09 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-02-24 15:23:32 -0800 |
| commit | c9e1f58818c2e6ac13296406125e43775c4daa55 (patch) | |
| tree | 38b8acc431f6375cff8b7bc2eeaf2d4fe2bc756d /board/freescale/p1010rdb/tlb.c | |
| parent | 27585bd3572f2743fef87adebd9e48b33483c4be (diff) | |
| download | u-boot-imx-c9e1f58818c2e6ac13296406125e43775c4daa55.zip u-boot-imx-c9e1f58818c2e6ac13296406125e43775c4daa55.tar.gz u-boot-imx-c9e1f58818c2e6ac13296406125e43775c4daa55.tar.bz2 | |
powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.
This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb/tlb.c')
| -rw-r--r-- | board/freescale/p1010rdb/tlb.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index a3d36b3..af40f97 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -73,10 +73,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1) + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) #endif }; |