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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-04-16 13:28:12 +0530 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 16:09:07 -0500 |
| commit | 0fa934d235c282e8efd119fc14a18315a8666930 (patch) | |
| tree | f5ba5143a55d85340127fcf34b6789c140628a89 /board/freescale/p1010rdb/tlb.c | |
| parent | 3a88179d03dfc41154e5bf12826c800dee864b7c (diff) | |
| download | u-boot-imx-0fa934d235c282e8efd119fc14a18315a8666930.zip u-boot-imx-0fa934d235c282e8efd119fc14a18315a8666930.tar.gz u-boot-imx-0fa934d235c282e8efd119fc14a18315a8666930.tar.bz2 | |
board/p1010rdb:Add NAND boot support using new SPL format
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
- remove nand_spl support for P1010RDB
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb/tlb.c')
| -rw-r--r-- | board/freescale/p1010rdb/tlb.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 4256bf4..7a8690a 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -43,16 +43,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), + SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_8K, 1), /* *I*G* - CCSRBAR */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SDCARD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 3, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_PCI +#ifndef CONFIG_PCI /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1) |