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| author | Wolfgang Denk <wd@denx.de> | 2012-04-30 16:45:56 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-04-30 16:45:56 +0200 |
| commit | 5f6db68b42024b51a9a1fddd7d4371d2af82c090 (patch) | |
| tree | 03c2bf7a546dddbac2cb9ab1c71bed56adfbf988 /board/freescale/p1010rdb/ddr.c | |
| parent | 04a9cb8c5947cec4356cf3b95a8ea3cc839dc540 (diff) | |
| parent | 822ad60f1c37a79659dc5889eb2993a462c9a95f (diff) | |
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
PowerPC: correct the SATA for p1/p2 rdb-pc platform
powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
powerpc/corenet_ds: Slave module for boot from SRIO
powerpc/corenet_ds: Master module for boot from SRIO
powerpc/corenet_ds: Document for the boot from SRIO
powerpc/corenet_ds: Correct the compilation errors about ENV
powerpc/srio: Rewrite the struct ccsr_rio
powerpc/85xx:Fix lds for nand boot debug info
powerpc/p2041rdb: add env in NAND support
powerpc/p2041rdb: add NAND and NAND boot support
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
powerpc/85xx:Avoid vector table compilation for nand_spl
powerpc/85xx:Fix IVORs addr after vector table relocation
powerpc/85xx:Avoid hardcoded vector address for IVORs
powerpc/p1023rds: Disable nor flash node and enable nand flash node
Diffstat (limited to 'board/freescale/p1010rdb/ddr.c')
| -rw-r--r-- | board/freescale/p1010rdb/ddr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index e5d8423..36c8545 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DDR_RAW_TIMING +#ifndef CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DRAM_SIZE 1024 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { @@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } -#else /* CONFIG_DDR_RAW_TIMING */ +#else /* CONFIG_SYS_DDR_RAW_TIMING */ /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } -#endif /* CONFIG_DDR_RAW_TIMING */ +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ |