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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-30 23:49:17 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-30 23:49:17 +0200 |
commit | 1c27059a2f7158a9c9a8778535b030935d75179d (patch) | |
tree | bf577d5c9f0da21c5d57feed1091214e54c39dec /board/freescale/p1010rdb/ddr.c | |
parent | 8f0732ac3dc3bdbbcada313dc4b4b38d5d2c376a (diff) | |
parent | 4668a086bb0a769b741e3a4ffab85f1c41c7cdb8 (diff) | |
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Merge remote-tracking branch 'u-boot/master'
Diffstat (limited to 'board/freescale/p1010rdb/ddr.c')
-rw-r--r-- | board/freescale/p1010rdb/ddr.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 10c5a42..6d00caf 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ if (cpu->soc_ver == SVR_P1014) { + ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; - ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; - ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; + /* divide SA and EA by two and then mask the rest so we don't + * write to reserved fields */ + ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |