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| author | Matthew McClintock <msm@freescale.com> | 2012-08-13 08:10:38 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 10:24:16 -0500 |
| commit | c8f9802a72030e783152040b07c3c7694f953dd3 (patch) | |
| tree | 1aa8ed1fe0386075afcf9628b87415598b2d36cd /board/freescale/p1010rdb/ddr.c | |
| parent | 9c6b47d53ed329b31c5f26e9ec710f67559c07f0 (diff) | |
| download | u-boot-imx-c8f9802a72030e783152040b07c3c7694f953dd3.zip u-boot-imx-c8f9802a72030e783152040b07c3c7694f953dd3.tar.gz u-boot-imx-c8f9802a72030e783152040b07c3c7694f953dd3.tar.bz2 | |
p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)
There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.
Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1010rdb/ddr.c')
| -rw-r--r-- | board/freescale/p1010rdb/ddr.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 10c5a42..6d00caf 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -147,10 +147,11 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ if (cpu->soc_ver == SVR_P1014) { + ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK; ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; - ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; - ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; - ddr_cfg_regs.ddr_sdram_cfg |= 0x001080000; + /* divide SA and EA by two and then mask the rest so we don't + * write to reserved fields */ + ddr_cfg_regs.cs[0].bnds = (CONFIG_SYS_DDR_CS0_BNDS >> 1) & 0x0fff0fff; } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |