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| author | Ye.Li <B37916@freescale.com> | 2015-03-09 11:59:08 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:02:00 +0800 |
| commit | 6af24d6b2166b1e43c5339e21f14c22309743dec (patch) | |
| tree | b1c4c16ffe6a388b18ecb87a8b84be8a839ce941 /board/freescale/mx7dsabresd | |
| parent | ce7798efc2b7a2d7cf458a2f5e3d263a73588b27 (diff) | |
| download | u-boot-imx-6af24d6b2166b1e43c5339e21f14c22309743dec.zip u-boot-imx-6af24d6b2166b1e43c5339e21f14c22309743dec.tar.gz u-boot-imx-6af24d6b2166b1e43c5339e21f14c22309743dec.tar.bz2 | |
MLK-10385-4 imx: mx7dsabresd: Add board codes for NAND flash support
Update board codes to support GPMI NAND flash. Since the GPMI NAND needs
board rework, it is disabled at default. Two ways to enable GPMI NAND:
1. Define CONFIG_SYS_BOOT_NAND for NAND boot case
2. Modify the line 306 in mx7dsabresd.h from QSPI to NAND.
#define CONFIG_SYS_USE_QSPI /* Enable the QSPI flash at default */
to
#define CONFIG_SYS_USE_NAND /* Enable the NAND flash at default */
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 5db03facf3add6a95728bc97ac2300003a103932)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'board/freescale/mx7dsabresd')
| -rw-r--r-- | board/freescale/mx7dsabresd/mx7dsabresd.c | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index ab6c21c..13aed0e 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -61,7 +61,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_DSE_3P3V_49OHM) #define EPDC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_40ohm | \ - PAD_CTL_DSE_3P3V_490HM) + PAD_CTL_DSE_3P3V_49OHM) #define QSPI_PAD_CTRL \ (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) @@ -70,6 +70,11 @@ DECLARE_GLOBAL_DATA_PTR; #define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + + #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC */ @@ -273,31 +278,29 @@ void iox74lv_set(int index) #ifdef CONFIG_SYS_USE_NAND static iomux_v3_cfg_t const gpmi_pads[] = { - MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), - MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1), - MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), }; static void setup_gpmi_nand(void) { - u32 target; - imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); /* |